mirror of https://gitlab.com/qemu-project/qemu
hw/usb/hcd-uhci: Expose generic prototypes to local header
Extract generic UHCI prototypes into a new "hcd-uhci.h" local header so we can reuse them in other units. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210309190802.830969-3-f4bug@amsat.org> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
This commit is contained in:
Philippe Mathieu-Daudé
Gerd Hoffmann
parent
f4c46916dc
commit
9a4e12a64d
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@ -40,6 +40,7 @@
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#include "qemu/main-loop.h"
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#include "qemu/module.h"
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#include "qom/object.h"
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#include "hcd-uhci.h"
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#define FRAME_TIMER_FREQ 1000
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@ -50,8 +51,6 @@
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#define MAX_FRAMES_PER_TICK (QH_VALID / 2)
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#define NB_PORTS 2
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enum {
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TD_RESULT_STOP_FRAME = 10,
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TD_RESULT_COMPLETE,
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@ -62,20 +61,8 @@ enum {
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typedef struct UHCIState UHCIState;
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typedef struct UHCIAsync UHCIAsync;
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typedef struct UHCIQueue UHCIQueue;
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typedef struct UHCIInfo UHCIInfo;
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typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass;
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struct UHCIInfo {
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const char *name;
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uint16_t vendor_id;
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uint16_t device_id;
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uint8_t revision;
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uint8_t irq_pin;
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void (*realize)(PCIDevice *dev, Error **errp);
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bool unplug;
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};
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struct UHCIPCIDeviceClass {
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PCIDeviceClass parent_class;
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UHCIInfo info;
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@ -107,43 +94,6 @@ struct UHCIQueue {
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int8_t valid;
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};
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typedef struct UHCIPort {
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USBPort port;
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uint16_t ctrl;
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} UHCIPort;
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struct UHCIState {
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PCIDevice dev;
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MemoryRegion io_bar;
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USBBus bus; /* Note unused when we're a companion controller */
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uint16_t cmd; /* cmd register */
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uint16_t status;
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uint16_t intr; /* interrupt enable register */
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uint16_t frnum; /* frame number */
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uint32_t fl_base_addr; /* frame list base address */
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uint8_t sof_timing;
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uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
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int64_t expire_time;
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QEMUTimer *frame_timer;
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QEMUBH *bh;
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uint32_t frame_bytes;
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uint32_t frame_bandwidth;
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bool completions_only;
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UHCIPort ports[NB_PORTS];
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/* Interrupts that should be raised at the end of the current frame. */
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uint32_t pending_int_mask;
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/* Active packets */
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QTAILQ_HEAD(, UHCIQueue) queues;
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uint8_t num_ports_vmstate;
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/* Properties */
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char *masterbus;
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uint32_t firstport;
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uint32_t maxframes;
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};
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typedef struct UHCI_TD {
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uint32_t link;
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uint32_t ctrl; /* see TD_CTRL_xxx */
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@ -160,10 +110,6 @@ static void uhci_async_cancel(UHCIAsync *async);
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static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td);
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static void uhci_resume(void *opaque);
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#define TYPE_UHCI "pci-uhci-usb"
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DECLARE_INSTANCE_CHECKER(UHCIState, UHCI,
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TYPE_UHCI)
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static inline int32_t uhci_queue_token(UHCI_TD *td)
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{
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if ((td->token & (0xf << 15)) == 0) {
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@ -1213,7 +1159,7 @@ static USBPortOps uhci_port_ops = {
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static USBBusOps uhci_bus_ops = {
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};
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static void usb_uhci_common_realize(PCIDevice *dev, Error **errp)
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void usb_uhci_common_realize(PCIDevice *dev, Error **errp)
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{
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Error *err = NULL;
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PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
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@ -1335,7 +1281,7 @@ static const TypeInfo uhci_pci_type_info = {
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},
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};
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static void uhci_data_class_init(ObjectClass *klass, void *data)
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void uhci_data_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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@ -0,0 +1,93 @@
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/*
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* USB UHCI controller emulation
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*
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* Copyright (c) 2005 Fabrice Bellard
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*
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* Copyright (c) 2008 Max Krasnyansky
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* Magor rewrite of the UHCI data structures parser and frame processor
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* Support for fully async operation and multiple outstanding transactions
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_USB_HCD_UHCI_H
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#define HW_USB_HCD_UHCI_H
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#include "exec/memory.h"
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#include "qemu/timer.h"
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#include "hw/pci/pci.h"
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#include "hw/usb.h"
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typedef struct UHCIQueue UHCIQueue;
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#define NB_PORTS 2
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typedef struct UHCIPort {
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USBPort port;
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uint16_t ctrl;
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} UHCIPort;
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typedef struct UHCIState {
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PCIDevice dev;
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MemoryRegion io_bar;
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USBBus bus; /* Note unused when we're a companion controller */
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uint16_t cmd; /* cmd register */
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uint16_t status;
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uint16_t intr; /* interrupt enable register */
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uint16_t frnum; /* frame number */
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uint32_t fl_base_addr; /* frame list base address */
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uint8_t sof_timing;
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uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
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int64_t expire_time;
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QEMUTimer *frame_timer;
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QEMUBH *bh;
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uint32_t frame_bytes;
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uint32_t frame_bandwidth;
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bool completions_only;
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UHCIPort ports[NB_PORTS];
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/* Interrupts that should be raised at the end of the current frame. */
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uint32_t pending_int_mask;
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/* Active packets */
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QTAILQ_HEAD(, UHCIQueue) queues;
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uint8_t num_ports_vmstate;
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/* Properties */
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char *masterbus;
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uint32_t firstport;
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uint32_t maxframes;
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} UHCIState;
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#define TYPE_UHCI "pci-uhci-usb"
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DECLARE_INSTANCE_CHECKER(UHCIState, UHCI, TYPE_UHCI)
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typedef struct UHCIInfo {
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const char *name;
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uint16_t vendor_id;
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uint16_t device_id;
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uint8_t revision;
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uint8_t irq_pin;
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void (*realize)(PCIDevice *dev, Error **errp);
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bool unplug;
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} UHCIInfo;
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void uhci_data_class_init(ObjectClass *klass, void *data);
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void usb_uhci_common_realize(PCIDevice *dev, Error **errp);
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#endif
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