raven: Implement non-contiguous I/O region
Remove now duplicated code from prep board. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
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49a4e21251
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9a1839164c
@ -54,8 +54,12 @@ typedef struct PRePPCIState {
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qemu_irq irq[PCI_NUM_PINS];
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PCIBus pci_bus;
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AddressSpace pci_io_as;
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MemoryRegion pci_io_non_contiguous;
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MemoryRegion pci_intack;
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RavenPCIState pci_dev;
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int contiguous_map;
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} PREPPCIState;
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#define BIOS_SIZE (1024 * 1024)
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@ -107,6 +111,71 @@ static const MemoryRegionOps PPC_intack_ops = {
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},
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};
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static inline hwaddr raven_io_address(PREPPCIState *s,
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hwaddr addr)
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{
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if (s->contiguous_map == 0) {
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/* 64 KB contiguous space for IOs */
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addr &= 0xFFFF;
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} else {
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/* 8 MB non-contiguous space for IOs */
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addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
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}
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/* FIXME: handle endianness switch */
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return addr;
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}
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static uint64_t raven_io_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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PREPPCIState *s = opaque;
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uint8_t buf[4];
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addr = raven_io_address(s, addr);
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address_space_read(&s->pci_io_as, addr, buf, size);
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if (size == 1) {
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return buf[0];
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} else if (size == 2) {
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return lduw_p(buf);
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} else if (size == 4) {
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return ldl_p(buf);
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} else {
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g_assert_not_reached();
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}
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}
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static void raven_io_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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PREPPCIState *s = opaque;
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uint8_t buf[4];
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addr = raven_io_address(s, addr);
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if (size == 1) {
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buf[0] = val;
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} else if (size == 2) {
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stw_p(buf, val);
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} else if (size == 4) {
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stl_p(buf, val);
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} else {
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g_assert_not_reached();
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}
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address_space_write(&s->pci_io_as, addr, buf, size);
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}
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static const MemoryRegionOps raven_io_ops = {
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.read = raven_io_read,
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.write = raven_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl.max_access_size = 4,
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.valid.unaligned = true,
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};
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static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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return (irq_num + (pci_dev->devfn >> 3)) & 1;
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@ -119,6 +188,13 @@ static void prep_set_irq(void *opaque, int irq_num, int level)
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qemu_set_irq(pic[irq_num] , level);
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}
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static void raven_change_gpio(void *opaque, int n, int level)
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{
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PREPPCIState *s = opaque;
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s->contiguous_map = level;
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}
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static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
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{
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SysBusDevice *dev = SYS_BUS_DEVICE(d);
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@ -133,6 +209,8 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
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sysbus_init_irq(dev, &s->irq[i]);
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}
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qdev_init_gpio_in(d, raven_change_gpio, 1);
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pci_bus_irqs(&s->pci_bus, prep_set_irq, prep_map_irq, s->irq, PCI_NUM_PINS);
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memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, s,
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@ -164,6 +242,13 @@ static void raven_pcihost_initfn(Object *obj)
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MemoryRegion *address_space_io = get_system_io();
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DeviceState *pci_dev;
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memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s,
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"pci-io-non-contiguous", 0x00800000);
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address_space_init(&s->pci_io_as, get_system_io(), "raven-io");
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/* CPU address space */
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memory_region_add_subregion_overlap(address_space_mem, 0x80000000,
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&s->pci_io_non_contiguous, 1);
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pci_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
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address_space_mem, address_space_io, 0, TYPE_PCI_BUS);
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h->bus = &s->pci_bus;
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@ -185,6 +185,7 @@ typedef struct sysctrl_t {
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uint8_t state;
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uint8_t syscontrol;
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int contiguous_map;
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qemu_irq contiguous_map_irq;
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int endian;
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} sysctrl_t;
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@ -253,6 +254,7 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
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case 0x0850:
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/* I/O map type register */
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sysctrl->contiguous_map = val & 0x01;
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qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map);
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break;
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default:
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printf("ERROR: unaffected IO port write: %04" PRIx32
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@ -327,91 +329,6 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
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return retval;
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}
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static inline hwaddr prep_IO_address(sysctrl_t *sysctrl,
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hwaddr addr)
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{
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if (sysctrl->contiguous_map == 0) {
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/* 64 KB contiguous space for IOs */
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addr &= 0xFFFF;
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} else {
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/* 8 MB non-contiguous space for IOs */
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addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
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}
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return addr;
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}
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static void PPC_prep_io_writeb (void *opaque, hwaddr addr,
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uint32_t value)
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{
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sysctrl_t *sysctrl = opaque;
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addr = prep_IO_address(sysctrl, addr);
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cpu_outb(addr, value);
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}
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static uint32_t PPC_prep_io_readb (void *opaque, hwaddr addr)
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{
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sysctrl_t *sysctrl = opaque;
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uint32_t ret;
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addr = prep_IO_address(sysctrl, addr);
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ret = cpu_inb(addr);
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return ret;
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}
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static void PPC_prep_io_writew (void *opaque, hwaddr addr,
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uint32_t value)
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{
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sysctrl_t *sysctrl = opaque;
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addr = prep_IO_address(sysctrl, addr);
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PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
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cpu_outw(addr, value);
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}
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static uint32_t PPC_prep_io_readw (void *opaque, hwaddr addr)
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{
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sysctrl_t *sysctrl = opaque;
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uint32_t ret;
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addr = prep_IO_address(sysctrl, addr);
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ret = cpu_inw(addr);
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PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
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return ret;
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}
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static void PPC_prep_io_writel (void *opaque, hwaddr addr,
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uint32_t value)
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{
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sysctrl_t *sysctrl = opaque;
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addr = prep_IO_address(sysctrl, addr);
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PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
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cpu_outl(addr, value);
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}
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static uint32_t PPC_prep_io_readl (void *opaque, hwaddr addr)
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{
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sysctrl_t *sysctrl = opaque;
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uint32_t ret;
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addr = prep_IO_address(sysctrl, addr);
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ret = cpu_inl(addr);
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PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
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return ret;
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}
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static const MemoryRegionOps PPC_prep_io_ops = {
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.old_mmio = {
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.read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl },
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.write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel },
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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#define NVRAM_SIZE 0x2000
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@ -458,7 +375,6 @@ static void ppc_prep_init(QEMUMachineInitArgs *args)
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CPUPPCState *env = NULL;
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nvram_t nvram;
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M48t59State *m48t59;
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MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1);
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PortioList *port_list = g_new(PortioList, 1);
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#if 0
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MemoryRegion *xcsr = g_new(MemoryRegion, 1);
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@ -567,6 +483,7 @@ static void ppc_prep_init(QEMUMachineInitArgs *args)
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fprintf(stderr, "Couldn't create PCI host controller.\n");
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exit(1);
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}
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sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0);
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/* PCI -> ISA bridge */
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pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
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@ -587,11 +504,6 @@ static void ppc_prep_init(QEMUMachineInitArgs *args)
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qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */
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qdev_init_nofail(dev);
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/* Register 8 MB of ISA IO space (needed for non-contiguous map) */
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memory_region_init_io(PPC_io_memory, NULL, &PPC_prep_io_ops, sysctrl,
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"ppc-io", 0x00800000);
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memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory);
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/* init basic PC hardware */
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pci_vga_init(pci_bus);
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