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target/riscv: Support configuarable marchid, mvendorid, mipid CSR values

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Allow user to set core's marchid, mvendorid, mipid CSRs through
-cpu command line option.

The default values of marchid and mipid are built with QEMU's version
numbers.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220422040436.2233-1-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2022-04-22 12:04:34 +08:00 committed by Alistair Francis
parent 58303fc0be
commit 9951ba948a
3 changed files with 47 additions and 4 deletions
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9
target/riscv/cpu.c
View File

@ -34,6 +34,11 @@
/* RISC-V CPU definitions */
#define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \
(QEMU_VERSION_MINOR << 8) | \
(QEMU_VERSION_MICRO))
#define RISCV_CPU_MIPID RISCV_CPU_MARCHID
static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
struct isa_ext_data {
@ -810,6 +815,10 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID),
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),

4
target/riscv/cpu.h
View File

@ -393,6 +393,10 @@ struct RISCVCPUConfig {
bool ext_zve32f;
bool ext_zve64f;
uint32_t mvendorid;
uint64_t marchid;
uint64_t mipid;
/* Vendor-specific custom extensions */
bool ext_XVentanaCondOps;

38
target/riscv/csr.c
View File

@ -612,6 +612,36 @@ static RISCVException write_ignore(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
target_ulong *val)
{
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
*val = cpu->cfg.mvendorid;
return RISCV_EXCP_NONE;
}
static RISCVException read_marchid(CPURISCVState *env, int csrno,
target_ulong *val)
{
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
*val = cpu->cfg.marchid;
return RISCV_EXCP_NONE;
}
static RISCVException read_mipid(CPURISCVState *env, int csrno,
target_ulong *val)
{
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
*val = cpu->cfg.mipid;
return RISCV_EXCP_NONE;
}
static RISCVException read_mhartid(CPURISCVState *env, int csrno,
target_ulong *val)
{
@ -3260,10 +3290,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
/* Machine Information Registers */
[CSR_MVENDORID] = { "mvendorid", any, read_zero },
[CSR_MARCHID] = { "marchid", any, read_zero },
[CSR_MIMPID] = { "mimpid", any, read_zero },
[CSR_MHARTID] = { "mhartid", any, read_mhartid },
[CSR_MVENDORID] = { "mvendorid", any, read_mvendorid },
[CSR_MARCHID] = { "marchid", any, read_marchid },
[CSR_MIMPID] = { "mimpid", any, read_mipid },
[CSR_MHARTID] = { "mhartid", any, read_mhartid },
[CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero,
.min_priv_ver = PRIV_VERSION_1_12_0 },