ppc/pnv: Improve pervasive topology calculation for big-core
Big (SMT8) cores have a complicated function to map the core, thread ID to pervasive topology (PIR). Fix this for power8, power9, and power10. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Caleb Schlossin <calebs@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Caleb Schlossin
Nicholas Piggin
parent
0b8893236e
commit
9940412ae4
71
hw/ppc/pnv.c
71
hw/ppc/pnv.c
@ -141,8 +141,10 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
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int smt_threads = CPU_CORE(pc)->nr_threads;
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CPUPPCState *env = &cpu->env;
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PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
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PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip);
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g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads);
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int i;
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uint32_t pir;
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uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
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0xffffffff, 0xffffffff};
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uint32_t tbfreq = PNV_TIMEBASE_FREQ;
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@ -153,15 +155,17 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
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char *nodename;
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int cpus_offset = get_cpus_node(fdt);
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nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
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pir = pnv_cc->chip_pir(chip, pc->hwid, 0);
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nodename = g_strdup_printf("%s@%x", dc->fw_name, pir);
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offset = fdt_add_subnode(fdt, cpus_offset, nodename);
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_FDT(offset);
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g_free(nodename);
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_FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
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_FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
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_FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
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_FDT((fdt_setprop_cell(fdt, offset, "reg", pir)));
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_FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir)));
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_FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
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_FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
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@ -233,7 +237,7 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
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/* Build interrupt servers properties */
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for (i = 0; i < smt_threads; i++) {
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servers_prop[i] = cpu_to_be32(pc->pir + i);
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servers_prop[i] = cpu_to_be32(pnv_cc->chip_pir(chip, pc->hwid, i));
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}
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_FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
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servers_prop, sizeof(*servers_prop) * smt_threads)));
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@ -241,9 +245,11 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
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return offset;
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}
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static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
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static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid,
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uint32_t nr_threads)
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{
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PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
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uint32_t pir = pcc->chip_pir(chip, hwid, 0);
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uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
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char *name;
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const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
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@ -257,6 +263,7 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
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rsize = sizeof(uint64_t) * 2 * nr_threads;
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reg = g_malloc(rsize);
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for (i = 0; i < nr_threads; i++) {
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/* We know P8 PIR is linear with thread id */
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reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
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reg[i * 2 + 1] = cpu_to_be64(0x1000);
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}
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@ -324,7 +331,7 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
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pa_features_207, sizeof(pa_features_207))));
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/* Interrupt Control Presenters (ICP). One per core. */
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pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
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pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads);
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}
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if (chip->ram_size) {
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@ -1075,9 +1082,10 @@ static void pnv_init(MachineState *machine)
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* 25:28 Core number
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* 29:31 Thread ID
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*/
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static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
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static uint32_t pnv_chip_pir_p8(PnvChip *chip, uint32_t core_id,
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uint32_t thread_id)
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{
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return (chip->chip_id << 7) | (core_id << 3);
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return (chip->chip_id << 7) | (core_id << 3) | thread_id;
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}
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static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
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@ -1129,14 +1137,37 @@ static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
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*
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* We only care about the lower bits. uint32_t is fine for the moment.
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*/
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static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
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static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint32_t core_id,
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uint32_t thread_id)
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{
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return (chip->chip_id << 8) | (core_id << 2);
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if (chip->nr_threads == 8) {
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return (chip->chip_id << 8) | ((thread_id & 1) << 2) | (core_id << 3) |
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(thread_id >> 1);
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} else {
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return (chip->chip_id << 8) | (core_id << 2) | thread_id;
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}
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}
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static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
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/*
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* 0:48 Reserved - Read as zeroes
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* 49:52 Node ID
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* 53:55 Chip ID
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* 56 Reserved - Read as zero
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* 57:59 Quad ID
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* 60 Core Chiplet Pair ID
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* 61:63 Thread/Core Chiplet ID t0-t2
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*
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* We only care about the lower bits. uint32_t is fine for the moment.
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*/
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static uint32_t pnv_chip_pir_p10(PnvChip *chip, uint32_t core_id,
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uint32_t thread_id)
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{
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return (chip->chip_id << 8) | (core_id << 2);
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if (chip->nr_threads == 8) {
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return (chip->chip_id << 8) | ((core_id / 4) << 4) |
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((core_id % 2) << 3) | thread_id;
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} else {
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return (chip->chip_id << 8) | (core_id << 2) | thread_id;
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}
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}
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static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
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@ -1315,7 +1346,7 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
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int core_hwid = CPU_CORE(pnv_core)->core_id;
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for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
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uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
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uint32_t pir = pcc->chip_pir(chip, core_hwid, j);
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PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
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memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
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@ -1428,7 +1459,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
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k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
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k->cores_mask = POWER8E_CORE_MASK;
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k->num_phbs = 3;
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k->core_pir = pnv_chip_core_pir_p8;
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k->chip_pir = pnv_chip_pir_p8;
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k->intc_create = pnv_chip_power8_intc_create;
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k->intc_reset = pnv_chip_power8_intc_reset;
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k->intc_destroy = pnv_chip_power8_intc_destroy;
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@ -1452,7 +1483,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
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k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
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k->cores_mask = POWER8_CORE_MASK;
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k->num_phbs = 3;
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k->core_pir = pnv_chip_core_pir_p8;
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k->chip_pir = pnv_chip_pir_p8;
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k->intc_create = pnv_chip_power8_intc_create;
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k->intc_reset = pnv_chip_power8_intc_reset;
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k->intc_destroy = pnv_chip_power8_intc_destroy;
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@ -1476,7 +1507,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
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k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
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k->cores_mask = POWER8_CORE_MASK;
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k->num_phbs = 4;
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k->core_pir = pnv_chip_core_pir_p8;
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k->chip_pir = pnv_chip_pir_p8;
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k->intc_create = pnv_chip_power8_intc_create;
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k->intc_reset = pnv_chip_power8_intc_reset;
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k->intc_destroy = pnv_chip_power8_intc_destroy;
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@ -1749,7 +1780,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
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k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
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k->cores_mask = POWER9_CORE_MASK;
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k->core_pir = pnv_chip_core_pir_p9;
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k->chip_pir = pnv_chip_pir_p9;
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k->intc_create = pnv_chip_power9_intc_create;
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k->intc_reset = pnv_chip_power9_intc_reset;
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k->intc_destroy = pnv_chip_power9_intc_destroy;
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@ -2061,7 +2092,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
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k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
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k->cores_mask = POWER10_CORE_MASK;
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k->core_pir = pnv_chip_core_pir_p10;
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k->chip_pir = pnv_chip_pir_p10;
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k->intc_create = pnv_chip_power10_intc_create;
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k->intc_reset = pnv_chip_power10_intc_reset;
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k->intc_destroy = pnv_chip_power10_intc_destroy;
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@ -2151,8 +2182,8 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
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chip->nr_threads, &error_fatal);
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object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID,
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core_hwid, &error_fatal);
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object_property_set_int(OBJECT(pnv_core), "pir",
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pcc->core_pir(chip, core_hwid), &error_fatal);
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object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid,
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&error_fatal);
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object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr,
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&error_fatal);
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object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip),
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@ -226,7 +226,7 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp,
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int thread_index)
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{
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CPUPPCState *env = &cpu->env;
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int core_pir;
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int core_hwid;
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ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
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ppc_spr_t *tir = &env->spr_cb[SPR_TIR];
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Error *local_err = NULL;
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@ -242,10 +242,10 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp,
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return;
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}
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core_pir = object_property_get_uint(OBJECT(pc), "pir", &error_abort);
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core_hwid = object_property_get_uint(OBJECT(pc), "hwid", &error_abort);
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tir->default_value = thread_index;
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pir->default_value = core_pir + thread_index;
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pir->default_value = pcc->chip_pir(pc->chip, core_hwid, thread_index);
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/* Set time-base frequency to 512 MHz */
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cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
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@ -342,7 +342,7 @@ static void pnv_core_unrealize(DeviceState *dev)
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}
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static Property pnv_core_properties[] = {
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DEFINE_PROP_UINT32("pir", PnvCore, pir, 0),
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DEFINE_PROP_UINT32("hwid", PnvCore, hwid, 0),
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DEFINE_PROP_UINT64("hrmor", PnvCore, hrmor, 0),
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DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *),
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DEFINE_PROP_END_OF_LIST(),
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@ -147,7 +147,7 @@ struct PnvChipClass {
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DeviceRealize parent_realize;
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uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
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uint32_t (*chip_pir)(PnvChip *chip, uint32_t core_id, uint32_t thread_id);
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void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
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void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
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void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
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@ -36,6 +36,7 @@ struct PnvCore {
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/*< public >*/
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PowerPCCPU **threads;
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uint32_t pir;
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uint32_t hwid;
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uint64_t hrmor;
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PnvChip *chip;
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@ -49,9 +49,6 @@ void helper_spr_core_write_generic(CPUPPCState *env, uint32_t sprn,
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CPUState *cs = env_cpu(env);
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CPUState *ccs;
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uint32_t nr_threads = cs->nr_threads;
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uint32_t core_id = env->spr[SPR_PIR] & ~(nr_threads - 1);
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assert(core_id == env->spr[SPR_PIR] - env->spr[SPR_TIR]);
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if (nr_threads == 1) {
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env->spr[sprn] = val;
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