target-arm: Translate with condexec bits from TB flags, not CPUState
When translating, the condexec bits for the TB are in the TB flags; the CPUState condexec bits may be different. This patch fixes https://bugs.launchpad.net/bugs/604872 where we might segfault if we took an exception in the middle of a TB with an IT block, because when we came to retranslate in cpu_restore_state() the CPUState condexec bits would have advanced compared to the start of the TB and we would generate different (wrong) code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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@ -9096,8 +9096,8 @@ static inline void gen_intermediate_code_internal(CPUState *env,
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dc->singlestep_enabled = env->singlestep_enabled;
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dc->singlestep_enabled = env->singlestep_enabled;
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dc->condjmp = 0;
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dc->condjmp = 0;
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dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
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dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
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dc->condexec_mask = (env->condexec_bits & 0xf) << 1;
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dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
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dc->condexec_cond = env->condexec_bits >> 4;
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dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
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#if !defined(CONFIG_USER_ONLY)
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#if !defined(CONFIG_USER_ONLY)
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if (IS_M(env)) {
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if (IS_M(env)) {
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dc->user = ((env->v7m.exception == 0) && (env->v7m.control & 1));
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dc->user = ((env->v7m.exception == 0) && (env->v7m.control & 1));
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@ -9126,7 +9126,7 @@ static inline void gen_intermediate_code_internal(CPUState *env,
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gen_icount_start();
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gen_icount_start();
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/* Reset the conditional execution bits immediately. This avoids
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/* Reset the conditional execution bits immediately. This avoids
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complications trying to do it at the end of the block. */
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complications trying to do it at the end of the block. */
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if (env->condexec_bits)
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if (dc->condexec_mask || dc->condexec_cond)
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{
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{
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TCGv tmp = new_tmp();
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TCGv tmp = new_tmp();
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tcg_gen_movi_i32(tmp, 0);
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tcg_gen_movi_i32(tmp, 0);
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