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ide: rename cmd_write to ctrl_write

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It's the Control register, part of the Control block -- Command is
misleading here. Rename all related functions and constants.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
This commit is contained in:
John Snow 2020-07-24 01:22:54 -04:00
parent 1d1c4bdb73
commit 98d9891223
7 changed files with 24 additions and 23 deletions
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12
hw/ide/core.c
View File

@ -2235,25 +2235,25 @@ uint32_t ide_status_read(void *opaque, uint32_t addr)
return ret; return ret;
} }
void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val) void ide_ctrl_write(void *opaque, uint32_t addr, uint32_t val)
{ {
IDEBus *bus = opaque; IDEBus *bus = opaque;
IDEState *s; IDEState *s;
int i; int i;
trace_ide_cmd_write(addr, val, bus); trace_ide_ctrl_write(addr, val, bus);
/* common for both drives */ /* common for both drives */
if (!(bus->cmd & IDE_CMD_RESET) && if (!(bus->cmd & IDE_CTRL_RESET) &&
(val & IDE_CMD_RESET)) { (val & IDE_CTRL_RESET)) {
/* reset low to high */ /* reset low to high */
for(i = 0;i < 2; i++) { for(i = 0;i < 2; i++) {
s = &bus->ifs[i]; s = &bus->ifs[i];
s->status = BUSY_STAT | SEEK_STAT; s->status = BUSY_STAT | SEEK_STAT;
s->error = 0x01; s->error = 0x01;
} }
} else if ((bus->cmd & IDE_CMD_RESET) && } else if ((bus->cmd & IDE_CTRL_RESET) &&
!(val & IDE_CMD_RESET)) { !(val & IDE_CTRL_RESET)) {
/* high to low */ /* high to low */
for(i = 0;i < 2; i++) { for(i = 0;i < 2; i++) {
s = &bus->ifs[i]; s = &bus->ifs[i];

2
hw/ide/ioport.c
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@ -46,7 +46,7 @@ static const MemoryRegionPortio ide_portio_list[] = {
}; };
static const MemoryRegionPortio ide_portio2_list[] = { static const MemoryRegionPortio ide_portio2_list[] = {
{ 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write }, { 0, 1, 1, .read = ide_status_read, .write = ide_ctrl_write },
PORTIO_END_OF_LIST(), PORTIO_END_OF_LIST(),
}; };

2
hw/ide/macio.c
View File

@ -329,7 +329,7 @@ static void pmac_ide_write(void *opaque, hwaddr addr, uint64_t val,
case 0x8: case 0x8:
case 0x16: case 0x16:
if (size == 1) { if (size == 1) {
ide_cmd_write(&d->bus, 0, val); ide_ctrl_write(&d->bus, 0, val);
} }
break; break;
case 0x20: case 0x20:

8
hw/ide/mmio.c
View File

@ -98,16 +98,16 @@ static uint64_t mmio_ide_status_read(void *opaque, hwaddr addr,
return ide_status_read(&s->bus, 0); return ide_status_read(&s->bus, 0);
} }
static void mmio_ide_cmd_write(void *opaque, hwaddr addr, static void mmio_ide_ctrl_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size) uint64_t val, unsigned size)
{ {
MMIOState *s = opaque; MMIOState *s = opaque;
ide_cmd_write(&s->bus, 0, val); ide_ctrl_write(&s->bus, 0, val);
} }
static const MemoryRegionOps mmio_ide_cs_ops = { static const MemoryRegionOps mmio_ide_cs_ops = {
.read = mmio_ide_status_read, .read = mmio_ide_status_read,
.write = mmio_ide_cmd_write, .write = mmio_ide_ctrl_write,
.endianness = DEVICE_LITTLE_ENDIAN, .endianness = DEVICE_LITTLE_ENDIAN,
}; };

12
hw/ide/pci.c
View File

@ -38,7 +38,7 @@
(IDE_RETRY_DMA | IDE_RETRY_PIO | \ (IDE_RETRY_DMA | IDE_RETRY_PIO | \
IDE_RETRY_READ | IDE_RETRY_FLUSH) IDE_RETRY_READ | IDE_RETRY_FLUSH)
static uint64_t pci_ide_cmd_read(void *opaque, hwaddr addr, unsigned size) static uint64_t pci_ide_status_read(void *opaque, hwaddr addr, unsigned size)
{ {
IDEBus *bus = opaque; IDEBus *bus = opaque;
@ -48,20 +48,20 @@ static uint64_t pci_ide_cmd_read(void *opaque, hwaddr addr, unsigned size)
return ide_status_read(bus, addr + 2); return ide_status_read(bus, addr + 2);
} }
static void pci_ide_cmd_write(void *opaque, hwaddr addr, static void pci_ide_ctrl_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size) uint64_t data, unsigned size)
{ {
IDEBus *bus = opaque; IDEBus *bus = opaque;
if (addr != 2 || size != 1) { if (addr != 2 || size != 1) {
return; return;
} }
ide_cmd_write(bus, addr + 2, data); ide_ctrl_write(bus, addr + 2, data);
} }
const MemoryRegionOps pci_ide_cmd_le_ops = { const MemoryRegionOps pci_ide_cmd_le_ops = {
.read = pci_ide_cmd_read, .read = pci_ide_status_read,
.write = pci_ide_cmd_write, .write = pci_ide_ctrl_write,
.endianness = DEVICE_LITTLE_ENDIAN, .endianness = DEVICE_LITTLE_ENDIAN,
}; };

2
hw/ide/trace-events
View File

@ -5,7 +5,7 @@
ide_ioport_read(uint32_t addr, const char *reg, uint32_t val, void *bus, void *s) "IDE PIO rd @ 0x%"PRIx32" (%s); val 0x%02"PRIx32"; bus %p IDEState %p" ide_ioport_read(uint32_t addr, const char *reg, uint32_t val, void *bus, void *s) "IDE PIO rd @ 0x%"PRIx32" (%s); val 0x%02"PRIx32"; bus %p IDEState %p"
ide_ioport_write(uint32_t addr, const char *reg, uint32_t val, void *bus, void *s) "IDE PIO wr @ 0x%"PRIx32" (%s); val 0x%02"PRIx32"; bus %p IDEState %p" ide_ioport_write(uint32_t addr, const char *reg, uint32_t val, void *bus, void *s) "IDE PIO wr @ 0x%"PRIx32" (%s); val 0x%02"PRIx32"; bus %p IDEState %p"
ide_status_read(uint32_t addr, uint32_t val, void *bus, void *s) "IDE PIO rd @ 0x%"PRIx32" (Alt Status); val 0x%02"PRIx32"; bus %p; IDEState %p" ide_status_read(uint32_t addr, uint32_t val, void *bus, void *s) "IDE PIO rd @ 0x%"PRIx32" (Alt Status); val 0x%02"PRIx32"; bus %p; IDEState %p"
ide_cmd_write(uint32_t addr, uint32_t val, void *bus) "IDE PIO wr @ 0x%"PRIx32" (Device Control); val 0x%02"PRIx32"; bus %p" ide_ctrl_write(uint32_t addr, uint32_t val, void *bus) "IDE PIO wr @ 0x%"PRIx32" (Device Control); val 0x%02"PRIx32"; bus %p"
# Warning: verbose # Warning: verbose
ide_data_readw(uint32_t addr, uint32_t val, void *bus, void *s) "IDE PIO rd @ 0x%"PRIx32" (Data: Word); val 0x%04"PRIx32"; bus %p; IDEState %p" ide_data_readw(uint32_t addr, uint32_t val, void *bus, void *s) "IDE PIO rd @ 0x%"PRIx32" (Data: Word); val 0x%04"PRIx32"; bus %p; IDEState %p"
ide_data_writew(uint32_t addr, uint32_t val, void *bus, void *s) "IDE PIO wr @ 0x%"PRIx32" (Data: Word); val 0x%04"PRIx32"; bus %p; IDEState %p" ide_data_writew(uint32_t addr, uint32_t val, void *bus, void *s) "IDE PIO wr @ 0x%"PRIx32" (Data: Word); val 0x%04"PRIx32"; bus %p; IDEState %p"

9
include/hw/ide/internal.h
View File

@ -57,8 +57,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(IDEBus, IDE_BUS)
#define REL 0x04 #define REL 0x04
#define TAG_MASK 0xf8 #define TAG_MASK 0xf8
#define IDE_CMD_RESET 0x04 /* Bits of Device Control register */
#define IDE_CMD_DISABLE_IRQ 0x02 #define IDE_CTRL_RESET 0x04
#define IDE_CTRL_DISABLE_IRQ 0x02
/* ACS-2 T13/2015-D Table B.2 Command codes */ /* ACS-2 T13/2015-D Table B.2 Command codes */
#define WIN_NOP 0x00 #define WIN_NOP 0x00
@ -559,7 +560,7 @@ static inline IDEState *idebus_active_if(IDEBus *bus)
static inline void ide_set_irq(IDEBus *bus) static inline void ide_set_irq(IDEBus *bus)
{ {
if (!(bus->cmd & IDE_CMD_DISABLE_IRQ)) { if (!(bus->cmd & IDE_CTRL_DISABLE_IRQ)) {
qemu_irq_raise(bus->irq); qemu_irq_raise(bus->irq);
} }
} }
@ -598,7 +599,7 @@ void ide_atapi_io_error(IDEState *s, int ret);
void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val); void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val);
uint32_t ide_ioport_read(void *opaque, uint32_t addr1); uint32_t ide_ioport_read(void *opaque, uint32_t addr1);
uint32_t ide_status_read(void *opaque, uint32_t addr); uint32_t ide_status_read(void *opaque, uint32_t addr);
void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val); void ide_ctrl_write(void *opaque, uint32_t addr, uint32_t val);
void ide_data_writew(void *opaque, uint32_t addr, uint32_t val); void ide_data_writew(void *opaque, uint32_t addr, uint32_t val);
uint32_t ide_data_readw(void *opaque, uint32_t addr); uint32_t ide_data_readw(void *opaque, uint32_t addr);
void ide_data_writel(void *opaque, uint32_t addr, uint32_t val); void ide_data_writel(void *opaque, uint32_t addr, uint32_t val);