hw/pci-host: Add emulation of Mai Logic Articia S
The Articia S is a generic chipset supporting several different CPUs that were among others used on some PPC boards. This is a minimal emulation of the parts needed for emulating the AmigaOne board. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Tested-by: Rene Engel <ReneEngel80@emailn.de> Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-ID: <83822787431701cf4d460298d3e3845f362e5da1.1698406922.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
BALATON Zoltan
Daniel Henrique Barboza
parent
462ad017ed
commit
97d3b2cd36
@ -73,6 +73,11 @@ config SH_PCI
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bool
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select PCI
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config ARTICIA
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bool
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select PCI
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select I8259
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config MV64361
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bool
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select PCI
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293
hw/pci-host/articia.c
Normal file
293
hw/pci-host/articia.c
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@ -0,0 +1,293 @@
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/*
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* Mai Logic Articia S emulation
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*
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* Copyright (c) 2023 BALATON Zoltan
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "hw/pci/pci_device.h"
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#include "hw/pci/pci_host.h"
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#include "hw/irq.h"
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#include "hw/i2c/bitbang_i2c.h"
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#include "hw/intc/i8259.h"
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#include "hw/pci-host/articia.h"
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/*
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* This is a minimal emulation of this chip as used in AmigaOne board.
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* Most features are missing but those are not needed by firmware and guests.
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*/
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OBJECT_DECLARE_SIMPLE_TYPE(ArticiaState, ARTICIA)
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OBJECT_DECLARE_SIMPLE_TYPE(ArticiaHostState, ARTICIA_PCI_HOST)
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struct ArticiaHostState {
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PCIDevice parent_obj;
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ArticiaState *as;
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};
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/* TYPE_ARTICIA */
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struct ArticiaState {
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PCIHostState parent_obj;
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qemu_irq irq[PCI_NUM_PINS];
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MemoryRegion io;
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MemoryRegion mem;
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MemoryRegion reg;
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bitbang_i2c_interface smbus;
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uint32_t gpio; /* bits 0-7 in, 8-15 out, 16-23 direction (0 in, 1 out) */
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hwaddr gpio_base;
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MemoryRegion gpio_reg;
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};
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static uint64_t articia_gpio_read(void *opaque, hwaddr addr, unsigned int size)
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{
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ArticiaState *s = opaque;
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return (s->gpio >> (addr * 8)) & 0xff;
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}
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static void articia_gpio_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned int size)
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{
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ArticiaState *s = opaque;
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uint32_t sh = addr * 8;
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if (addr == 0) {
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/* in bits read only? */
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return;
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}
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if ((s->gpio & (0xff << sh)) != (val & 0xff) << sh) {
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s->gpio &= ~(0xff << sh | 0xff);
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s->gpio |= (val & 0xff) << sh;
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s->gpio |= bitbang_i2c_set(&s->smbus, BITBANG_I2C_SDA,
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s->gpio & BIT(16) ?
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!!(s->gpio & BIT(8)) : 1);
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if ((s->gpio & BIT(17))) {
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s->gpio &= ~BIT(0);
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s->gpio |= bitbang_i2c_set(&s->smbus, BITBANG_I2C_SCL,
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!!(s->gpio & BIT(9)));
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}
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}
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}
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static const MemoryRegionOps articia_gpio_ops = {
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.read = articia_gpio_read,
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.write = articia_gpio_write,
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.valid.min_access_size = 1,
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.valid.max_access_size = 1,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static uint64_t articia_reg_read(void *opaque, hwaddr addr, unsigned int size)
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{
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ArticiaState *s = opaque;
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uint64_t ret = UINT_MAX;
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switch (addr) {
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case 0xc00cf8:
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ret = pci_host_conf_le_ops.read(PCI_HOST_BRIDGE(s), 0, size);
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break;
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case 0xe00cfc ... 0xe00cff:
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ret = pci_host_data_le_ops.read(PCI_HOST_BRIDGE(s), addr - 0xe00cfc, size);
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break;
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case 0xf00000:
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ret = pic_read_irq(isa_pic);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register read 0x%"
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HWADDR_PRIx " %d\n", __func__, addr, size);
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break;
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}
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return ret;
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}
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static void articia_reg_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned int size)
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{
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ArticiaState *s = opaque;
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switch (addr) {
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case 0xc00cf8:
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pci_host_conf_le_ops.write(PCI_HOST_BRIDGE(s), 0, val, size);
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break;
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case 0xe00cfc ... 0xe00cff:
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pci_host_data_le_ops.write(PCI_HOST_BRIDGE(s), addr, val, size);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register write 0x%"
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HWADDR_PRIx " %d <- %"PRIx64"\n", __func__, addr, size, val);
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break;
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}
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}
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static const MemoryRegionOps articia_reg_ops = {
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.read = articia_reg_read,
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.write = articia_reg_write,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void articia_pcihost_set_irq(void *opaque, int n, int level)
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{
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ArticiaState *s = opaque;
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qemu_set_irq(s->irq[n], level);
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}
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/*
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* AmigaOne SE PCI slot to IRQ routing
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*
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* repository: https://source.denx.de/u-boot/custodians/u-boot-avr32.git
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* refspec: v2010.06
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* file: board/MAI/AmigaOneG3SE/articiaS_pci.c
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*/
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static int amigaone_pcihost_bus0_map_irq(PCIDevice *pdev, int pin)
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{
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int devfn_slot = PCI_SLOT(pdev->devfn);
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switch (devfn_slot) {
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case 6: /* On board ethernet */
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return 3;
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case 7: /* South bridge */
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return pin;
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default: /* PCI Slot 1 Devfn slot 8, Slot 2 Devfn 9, Slot 3 Devfn 10 */
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return pci_swizzle(devfn_slot, pin);
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}
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}
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static void articia_realize(DeviceState *dev, Error **errp)
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{
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ArticiaState *s = ARTICIA(dev);
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PCIHostState *h = PCI_HOST_BRIDGE(dev);
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PCIDevice *pdev;
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bitbang_i2c_init(&s->smbus, i2c_init_bus(dev, "smbus"));
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memory_region_init_io(&s->gpio_reg, OBJECT(s), &articia_gpio_ops, s,
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TYPE_ARTICIA, 4);
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memory_region_init(&s->mem, OBJECT(dev), "pci-mem", UINT64_MAX);
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memory_region_init(&s->io, OBJECT(dev), "pci-io", 0xc00000);
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memory_region_init_io(&s->reg, OBJECT(s), &articia_reg_ops, s,
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TYPE_ARTICIA, 0x1000000);
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memory_region_add_subregion_overlap(&s->reg, 0, &s->io, 1);
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/* devfn_min is 8 that matches first PCI slot in AmigaOne */
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h->bus = pci_register_root_bus(dev, NULL, articia_pcihost_set_irq,
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amigaone_pcihost_bus0_map_irq, dev, &s->mem,
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&s->io, PCI_DEVFN(8, 0), 4, TYPE_PCI_BUS);
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pdev = pci_create_simple_multifunction(h->bus, PCI_DEVFN(0, 0),
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TYPE_ARTICIA_PCI_HOST);
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ARTICIA_PCI_HOST(pdev)->as = s;
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pci_create_simple(h->bus, PCI_DEVFN(0, 1), TYPE_ARTICIA_PCI_BRIDGE);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->reg);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mem);
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qdev_init_gpio_out(dev, s->irq, ARRAY_SIZE(s->irq));
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}
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static void articia_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = articia_realize;
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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}
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/* TYPE_ARTICIA_PCI_HOST */
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static void articia_pci_host_cfg_write(PCIDevice *d, uint32_t addr,
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uint32_t val, int len)
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{
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ArticiaState *s = ARTICIA_PCI_HOST(d)->as;
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pci_default_write_config(d, addr, val, len);
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switch (addr) {
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case 0x40:
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s->gpio_base = val;
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break;
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case 0x44:
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if (val != 0x11) {
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/* FIXME what do the bits actually mean? */
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break;
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}
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if (memory_region_is_mapped(&s->gpio_reg)) {
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memory_region_del_subregion(&s->io, &s->gpio_reg);
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}
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memory_region_add_subregion(&s->io, s->gpio_base + 0x38, &s->gpio_reg);
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break;
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}
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}
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static void articia_pci_host_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->config_write = articia_pci_host_cfg_write;
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k->vendor_id = 0x10cc;
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k->device_id = 0x0660;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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/*
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* PCI-facing part of the host bridge,
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* not usable without the host-facing part
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*/
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dc->user_creatable = false;
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}
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/* TYPE_ARTICIA_PCI_BRIDGE */
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static void articia_pci_bridge_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->vendor_id = 0x10cc;
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k->device_id = 0x0661;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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/*
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* PCI-facing part of the host bridge,
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* not usable without the host-facing part
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*/
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dc->user_creatable = false;
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}
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static const TypeInfo articia_types[] = {
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{
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.name = TYPE_ARTICIA,
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.parent = TYPE_PCI_HOST_BRIDGE,
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.instance_size = sizeof(ArticiaState),
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.class_init = articia_class_init,
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},
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{
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.name = TYPE_ARTICIA_PCI_HOST,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(ArticiaHostState),
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.class_init = articia_pci_host_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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},
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{
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.name = TYPE_ARTICIA_PCI_BRIDGE,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIDevice),
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.class_init = articia_pci_bridge_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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},
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};
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DEFINE_TYPES(articia_types)
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@ -20,6 +20,8 @@ pci_ss.add(when: 'CONFIG_GRACKLE_PCI', if_true: files('grackle.c'))
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pci_ss.add(when: 'CONFIG_UNIN_PCI', if_true: files('uninorth.c'))
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# PowerPC E500 boards
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pci_ss.add(when: 'CONFIG_PPCE500_PCI', if_true: files('ppce500.c'))
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# AmigaOne
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pci_ss.add(when: 'CONFIG_ARTICIA', if_true: files('articia.c'))
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# Pegasos2
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pci_ss.add(when: 'CONFIG_MV64361', if_true: files('mv64361.c'))
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17
include/hw/pci-host/articia.h
Normal file
17
include/hw/pci-host/articia.h
Normal file
@ -0,0 +1,17 @@
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/*
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* Mai Logic Articia S emulation
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*
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* Copyright (c) 2023 BALATON Zoltan
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*
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*/
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#ifndef ARTICIA_H
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#define ARTICIA_H
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#define TYPE_ARTICIA "articia"
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#define TYPE_ARTICIA_PCI_HOST "articia-pci-host"
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#define TYPE_ARTICIA_PCI_BRIDGE "articia-pci-bridge"
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#endif
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