target/arm: Allow VFP and Neon to be disabled via a CPU property
Allow VFP and neon to be disabled via a CPU property. As with the "pmu" property, we only allow these features to be removed from CPUs which have it by default, not added to CPUs which don't have it. The primary motivation here is to be able to optionally create Cortex-M33 CPUs with no FPU, but we provide switches for both VFP and Neon because the two interact: * AArch64 can't have one without the other * Some ID register fields only change if both are disabled Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20190517174046.11146-2-peter.maydell@linaro.org
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150
target/arm/cpu.c
150
target/arm/cpu.c
@ -763,6 +763,12 @@ static Property arm_cpu_cfgend_property =
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static Property arm_cpu_has_pmu_property =
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static Property arm_cpu_has_pmu_property =
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DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
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DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
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static Property arm_cpu_has_vfp_property =
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DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
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static Property arm_cpu_has_neon_property =
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DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
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static Property arm_cpu_has_mpu_property =
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static Property arm_cpu_has_mpu_property =
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DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
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DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
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@ -803,6 +809,13 @@ void arm_cpu_post_init(Object *obj)
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if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
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if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
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set_feature(&cpu->env, ARM_FEATURE_PMSA);
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set_feature(&cpu->env, ARM_FEATURE_PMSA);
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}
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}
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/* Similarly for the VFP feature bits */
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if (arm_feature(&cpu->env, ARM_FEATURE_VFP4)) {
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set_feature(&cpu->env, ARM_FEATURE_VFP3);
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}
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if (arm_feature(&cpu->env, ARM_FEATURE_VFP3)) {
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set_feature(&cpu->env, ARM_FEATURE_VFP);
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}
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if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
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if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
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arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
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arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
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@ -847,6 +860,27 @@ void arm_cpu_post_init(Object *obj)
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&error_abort);
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&error_abort);
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}
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}
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/*
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* Allow user to turn off VFP and Neon support, but only for TCG --
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* KVM does not currently allow us to lie to the guest about its
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* ID/feature registers, so the guest always sees what the host has.
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*/
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if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
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cpu->has_vfp = true;
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if (!kvm_enabled()) {
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qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property,
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&error_abort);
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}
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}
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if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
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cpu->has_neon = true;
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if (!kvm_enabled()) {
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qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property,
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&error_abort);
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}
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}
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if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
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if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
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qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
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qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
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&error_abort);
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&error_abort);
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@ -956,6 +990,116 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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return;
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return;
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}
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}
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if (arm_feature(env, ARM_FEATURE_AARCH64) &&
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cpu->has_vfp != cpu->has_neon) {
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/*
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* This is an architectural requirement for AArch64; AArch32 is
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* more flexible and permits VFP-no-Neon and Neon-no-VFP.
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*/
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error_setg(errp,
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"AArch64 CPUs must have both VFP and Neon or neither");
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return;
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}
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if (!cpu->has_vfp) {
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uint64_t t;
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uint32_t u;
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unset_feature(env, ARM_FEATURE_VFP);
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unset_feature(env, ARM_FEATURE_VFP3);
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unset_feature(env, ARM_FEATURE_VFP4);
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t = cpu->isar.id_aa64isar1;
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t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
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cpu->isar.id_aa64isar1 = t;
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t = cpu->isar.id_aa64pfr0;
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t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf);
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cpu->isar.id_aa64pfr0 = t;
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u = cpu->isar.id_isar6;
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u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
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cpu->isar.id_isar6 = u;
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u = cpu->isar.mvfr0;
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u = FIELD_DP32(u, MVFR0, FPSP, 0);
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u = FIELD_DP32(u, MVFR0, FPDP, 0);
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u = FIELD_DP32(u, MVFR0, FPTRAP, 0);
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u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0);
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u = FIELD_DP32(u, MVFR0, FPSQRT, 0);
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u = FIELD_DP32(u, MVFR0, FPSHVEC, 0);
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u = FIELD_DP32(u, MVFR0, FPROUND, 0);
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cpu->isar.mvfr0 = u;
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u = cpu->isar.mvfr1;
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u = FIELD_DP32(u, MVFR1, FPFTZ, 0);
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u = FIELD_DP32(u, MVFR1, FPDNAN, 0);
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u = FIELD_DP32(u, MVFR1, FPHP, 0);
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cpu->isar.mvfr1 = u;
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u = cpu->isar.mvfr2;
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u = FIELD_DP32(u, MVFR2, FPMISC, 0);
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cpu->isar.mvfr2 = u;
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}
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if (!cpu->has_neon) {
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uint64_t t;
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uint32_t u;
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unset_feature(env, ARM_FEATURE_NEON);
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t = cpu->isar.id_aa64isar0;
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t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
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cpu->isar.id_aa64isar0 = t;
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t = cpu->isar.id_aa64isar1;
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t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0);
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cpu->isar.id_aa64isar1 = t;
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t = cpu->isar.id_aa64pfr0;
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t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf);
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cpu->isar.id_aa64pfr0 = t;
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u = cpu->isar.id_isar5;
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u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
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u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
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cpu->isar.id_isar5 = u;
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u = cpu->isar.id_isar6;
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u = FIELD_DP32(u, ID_ISAR6, DP, 0);
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u = FIELD_DP32(u, ID_ISAR6, FHM, 0);
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cpu->isar.id_isar6 = u;
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u = cpu->isar.mvfr1;
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u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
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u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
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u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
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u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
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u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
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cpu->isar.mvfr1 = u;
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u = cpu->isar.mvfr2;
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u = FIELD_DP32(u, MVFR2, SIMDMISC, 0);
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cpu->isar.mvfr2 = u;
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}
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if (!cpu->has_neon && !cpu->has_vfp) {
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uint64_t t;
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uint32_t u;
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t = cpu->isar.id_aa64isar0;
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t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0);
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cpu->isar.id_aa64isar0 = t;
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t = cpu->isar.id_aa64isar1;
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t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0);
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cpu->isar.id_aa64isar1 = t;
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u = cpu->isar.mvfr0;
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u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
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cpu->isar.mvfr0 = u;
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}
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/* Some features automatically imply others: */
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/* Some features automatically imply others: */
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if (arm_feature(env, ARM_FEATURE_V8)) {
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if (arm_feature(env, ARM_FEATURE_V8)) {
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if (arm_feature(env, ARM_FEATURE_M)) {
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if (arm_feature(env, ARM_FEATURE_M)) {
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@ -1016,12 +1160,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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if (arm_feature(env, ARM_FEATURE_V5)) {
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if (arm_feature(env, ARM_FEATURE_V5)) {
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set_feature(env, ARM_FEATURE_V4T);
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set_feature(env, ARM_FEATURE_V4T);
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}
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}
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if (arm_feature(env, ARM_FEATURE_VFP4)) {
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set_feature(env, ARM_FEATURE_VFP3);
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}
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if (arm_feature(env, ARM_FEATURE_VFP3)) {
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set_feature(env, ARM_FEATURE_VFP);
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}
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if (arm_feature(env, ARM_FEATURE_LPAE)) {
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if (arm_feature(env, ARM_FEATURE_LPAE)) {
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set_feature(env, ARM_FEATURE_V7MP);
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set_feature(env, ARM_FEATURE_V7MP);
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set_feature(env, ARM_FEATURE_PXN);
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set_feature(env, ARM_FEATURE_PXN);
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@ -786,6 +786,10 @@ struct ARMCPU {
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bool has_el3;
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bool has_el3;
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/* CPU has PMU (Performance Monitor Unit) */
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/* CPU has PMU (Performance Monitor Unit) */
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bool has_pmu;
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bool has_pmu;
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/* CPU has VFP */
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bool has_vfp;
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/* CPU has Neon */
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bool has_neon;
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/* CPU has memory protection unit */
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/* CPU has memory protection unit */
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bool has_mpu;
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bool has_mpu;
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