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target/openrisc: Fix FPCSR mask to allow setting DZF

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The mask used when setting FPCSR allows setting bits 10 to 1.  However,
OpenRISC has flags and config bits in 11 to 1, 11 being Divide by Zero
Flag (DZF).  This seems like an off-by-one bug.

This was found when testing the GLIBC test suite which has test cases to
set and clear all bits.

Signed-off-by: Stafford Horne <shorne@gmail.com>
Message-Id: <20200110212843.27335-1-shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Stafford Horne 2020-01-11 06:28:43 +09:00 committed by Richard Henderson
parent 28b58f19d2
commit 97a254b3f0
1 changed files with 1 additions and 1 deletions
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2
target/openrisc/fpu_helper.c
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@ -70,7 +70,7 @@ void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val)
float_round_down
};
env->fpcsr = val & 0x7ff;
env->fpcsr = val & 0xfff;
set_float_rounding_mode(rm_to_sf[extract32(val, 1, 2)], &env->fp_status);
}