diff --git a/target-mips/op.c b/target-mips/op.c
index 1e2dbc8c21..aec6a022f2 100644
--- a/target-mips/op.c
+++ b/target-mips/op.c
@@ -2126,7 +2126,7 @@ void op_deret (void)
 void op_rdhwr_cpunum(void)
 {
     if (!(env->hflags & MIPS_HFLAG_UM) ||
-	(env->CP0_HWREna & (1 << 0)) ||
+        (env->CP0_HWREna & (1 << 0)) ||
         (env->CP0_Status & (1 << CP0St_CU0)))
         T0 = env->CP0_EBase & 0x3ff;
     else
@@ -2137,7 +2137,7 @@ void op_rdhwr_cpunum(void)
 void op_rdhwr_synci_step(void)
 {
     if (!(env->hflags & MIPS_HFLAG_UM) ||
-	(env->CP0_HWREna & (1 << 1)) ||
+        (env->CP0_HWREna & (1 << 1)) ||
         (env->CP0_Status & (1 << CP0St_CU0)))
         T0 = env->SYNCI_Step;
     else
@@ -2148,7 +2148,7 @@ void op_rdhwr_synci_step(void)
 void op_rdhwr_cc(void)
 {
     if (!(env->hflags & MIPS_HFLAG_UM) ||
-	(env->CP0_HWREna & (1 << 2)) ||
+        (env->CP0_HWREna & (1 << 2)) ||
         (env->CP0_Status & (1 << CP0St_CU0)))
         T0 = env->CP0_Count;
     else
@@ -2159,7 +2159,7 @@ void op_rdhwr_cc(void)
 void op_rdhwr_ccres(void)
 {
     if (!(env->hflags & MIPS_HFLAG_UM) ||
-	(env->CP0_HWREna & (1 << 3)) ||
+        (env->CP0_HWREna & (1 << 3)) ||
         (env->CP0_Status & (1 << CP0St_CU0)))
         T0 = env->CCRes;
     else
@@ -2167,28 +2167,6 @@ void op_rdhwr_ccres(void)
     RETURN();
 }
 
-void op_rdhwr_unimpl30(void)
-{
-    if (!(env->hflags & MIPS_HFLAG_UM) ||
-	(env->CP0_HWREna & (1 << 30)) ||
-        (env->CP0_Status & (1 << CP0St_CU0)))
-        T0 = 0;
-    else
-        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
-    RETURN();
-}
-
-void op_rdhwr_unimpl31(void)
-{
-    if (!(env->hflags & MIPS_HFLAG_UM) ||
-	(env->CP0_HWREna & (1 << 31)) ||
-        (env->CP0_Status & (1 << CP0St_CU0)))
-        T0 = 0;
-    else
-        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
-    RETURN();
-}
-
 void op_save_state (void)
 {
     env->hflags = PARAM1;
diff --git a/target-mips/translate.c b/target-mips/translate.c
index fd11e1b8df..57527a5e96 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -4825,32 +4825,26 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
         case OPC_RDHWR:
             switch (rd) {
             case 0:
+                save_cpu_state(ctx, 1);
                 gen_op_rdhwr_cpunum();
                 break;
             case 1:
+                save_cpu_state(ctx, 1);
                 gen_op_rdhwr_synci_step();
                 break;
             case 2:
+                save_cpu_state(ctx, 1);
                 gen_op_rdhwr_cc();
                 break;
             case 3:
+                save_cpu_state(ctx, 1);
                 gen_op_rdhwr_ccres();
                 break;
             case 29:
 #if defined (CONFIG_USER_ONLY)
                 gen_op_tls_value ();
-#else
-                generate_exception(ctx, EXCP_RI);
+                break;
 #endif
-                break;
-            case 30:
-                /* Implementation dependent */;
-                gen_op_rdhwr_unimpl30();
-                break;
-            case 31:
-                /* Implementation dependent */;
-                gen_op_rdhwr_unimpl31();
-                break;
             default:            /* Invalid */
                 MIPS_INVAL("rdhwr");
                 generate_exception(ctx, EXCP_RI);