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target/arm: Fix do_predset for large VL

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Use MAKE_64BIT_MASK instead of open-coding.  Remove an odd
vector size check that is unlikely to be more profitable
than 3 64-bit integer stores.  Correct the iteration for WORD
to avoid writing too much data.

Fixes RISU tests of PTRUE for VL 256.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180705191929.30773-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2018-07-09 14:51:34 +01:00 committed by Peter Maydell
parent 499748d768
commit 973558a3f8
1 changed files with 2 additions and 8 deletions
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10
target/arm/translate-sve.c
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@ -1438,7 +1438,7 @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
setsz = numelem << esz;
lastword = word = pred_esz_masks[esz];
if (setsz % 64) {
lastword &= ~(-1ull << (setsz % 64));
lastword &= MAKE_64BIT_MASK(0, setsz % 64);
}
}
@ -1457,19 +1457,13 @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word);
goto done;
}
if (oprsz * 8 == setsz + 8) {
tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word);
tcg_gen_movi_i64(t, 0);
tcg_gen_st_i64(t, cpu_env, ofs + oprsz - 8);
goto done;
}
}
setsz /= 8;
fullsz /= 8;
tcg_gen_movi_i64(t, word);
for (i = 0; i < setsz; i += 8) {
for (i = 0; i < QEMU_ALIGN_DOWN(setsz, 8); i += 8) {
tcg_gen_st_i64(t, cpu_env, ofs + i);
}
if (lastword != word) {