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target/arm: Implement SVE Stack Allocation Group

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2018-05-18 17:48:09 +01:00 committed by Peter Maydell
parent 9a56c9c3a9
commit 96f922cccc
2 changed files with 39 additions and 0 deletions
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12
target/arm/sve.decode
View File

@ -84,6 +84,9 @@
# One register operand, with governing predicate, vector element size # One register operand, with governing predicate, vector element size
@rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz
# Two register operands with a 6-bit signed immediate.
@rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri
# Two register operand, one immediate operand, with predicate, # Two register operand, one immediate operand, with predicate,
# element size encoded as TSZHL. User must fill in imm. # element size encoded as TSZHL. User must fill in imm.
@rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \ @rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \
@ -238,6 +241,15 @@ INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5
# SVE index generation (register start, register increment) # SVE index generation (register start, register increment)
INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm
### SVE Stack Allocation Group
# SVE stack frame adjustment
ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6
ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6
# SVE stack frame size
RDVL 00000100 101 11111 01010 imm:s6 rd:5
### SVE Predicate Logical Operations Group ### SVE Predicate Logical Operations Group
# SVE predicate logical operations # SVE predicate logical operations

27
target/arm/translate-sve.c
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@ -781,6 +781,33 @@ static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a, uint32_t insn)
return true; return true;
} }
/*
*** SVE Stack Allocation Group
*/
static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a, uint32_t insn)
{
TCGv_i64 rd = cpu_reg_sp(s, a->rd);
TCGv_i64 rn = cpu_reg_sp(s, a->rn);
tcg_gen_addi_i64(rd, rn, a->imm * vec_full_reg_size(s));
return true;
}
static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a, uint32_t insn)
{
TCGv_i64 rd = cpu_reg_sp(s, a->rd);
TCGv_i64 rn = cpu_reg_sp(s, a->rn);
tcg_gen_addi_i64(rd, rn, a->imm * pred_full_reg_size(s));
return true;
}
static bool trans_RDVL(DisasContext *s, arg_RDVL *a, uint32_t insn)
{
TCGv_i64 reg = cpu_reg(s, a->rd);
tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s));
return true;
}
/* /*
*** SVE Predicate Logical Operations Group *** SVE Predicate Logical Operations Group
*/ */