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target/riscv/csr.c: simplify mctr()

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Use riscv_cpu_cfg() to retrieve pmu_num.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230224174520.92490-3-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-02-24 14:45:18 -03:00 committed by Palmer Dabbelt
parent 3c7d54f945
commit 96b1b00058
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GPG Key ID: 2E1319F35FBB1889
1 changed files with 2 additions and 3 deletions
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target/riscv/csr.c
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@ -165,8 +165,7 @@ static RISCVException ctr32(CPURISCVState *env, int csrno)
#if !defined(CONFIG_USER_ONLY)
static RISCVException mctr(CPURISCVState *env, int csrno)
{
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
int pmu_num = riscv_cpu_cfg(env)->pmu_num;
int ctr_index;
int base_csrno = CSR_MHPMCOUNTER3;
@ -175,7 +174,7 @@ static RISCVException mctr(CPURISCVState *env, int csrno)
base_csrno += 0x80;
}
ctr_index = csrno - base_csrno;
if (!cpu->cfg.pmu_num || ctr_index >= cpu->cfg.pmu_num) {
if (!pmu_num || ctr_index >= pmu_num) {
/* The PMU is not enabled or counter is out of range*/
return RISCV_EXCP_ILLEGAL_INST;
}