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Use correct types to enable > 2G support, based on a patch from

Browse Source 
Anthony Liguori.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4238 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2008-04-22 20:37:34 +00:00
parent acb98efbbf
commit 967032c3d5
36 changed files with 153 additions and 98 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
cpu-all.h
View File

@ -700,7 +700,7 @@ static inline void stfq_be_p(void *ptr, float64 v)
/* page related stuff */
#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
#define TARGET_PAGE_SIZE (1UL << TARGET_PAGE_BITS)
#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
@ -806,12 +806,16 @@ int cpu_inw(CPUState *env, int addr);
int cpu_inl(CPUState *env, int addr);
#endif
/* address in the RAM (different from a physical address) */
typedef unsigned long ram_addr_t;
/* memory API */
extern int phys_ram_size;
extern ram_addr_t phys_ram_size;
extern int phys_ram_fd;
extern uint8_t *phys_ram_base;
extern uint8_t *phys_ram_dirty;
extern ram_addr_t ram_size;
/* physical memory access */
#define TLB_INVALID_MASK (1 << 3)
@ -833,10 +837,10 @@ typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t
typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
void cpu_register_physical_memory(target_phys_addr_t start_addr,
unsigned long size,
unsigned long phys_offset);
uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr);
ram_addr_t qemu_ram_alloc(unsigned int size);
ram_addr_t size,
ram_addr_t phys_offset);
ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
ram_addr_t qemu_ram_alloc(ram_addr_t);
void qemu_ram_free(ram_addr_t addr);
int cpu_register_io_memory(int io_index,
CPUReadMemoryFunc **mem_read,

3
cpu-defs.h
View File

@ -76,9 +76,6 @@ typedef uint64_t target_phys_addr_t;
#error TARGET_PHYS_ADDR_BITS undefined
#endif
/* address in the RAM (different from a physical address) */
typedef unsigned long ram_addr_t;
#define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
#define EXCP_INTERRUPT 0x10000 /* async interruption */

2
exec-all.h
View File

@ -82,7 +82,7 @@ int cpu_restore_state_copy(struct TranslationBlock *tb,
void cpu_resume_from_signal(CPUState *env1, void *puc);
void cpu_exec_init(CPUState *env);
int page_unprotect(target_ulong address, unsigned long pc, void *puc);
void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
int is_cpu_write_access);
void tb_invalidate_page_range(target_ulong start, target_ulong end);
void tlb_flush_page(CPUState *env, target_ulong addr);

51
exec.c
View File

@ -74,6 +74,10 @@
#define TARGET_VIRT_ADDR_SPACE_BITS 42
#elif defined(TARGET_PPC64)
#define TARGET_PHYS_ADDR_SPACE_BITS 42
#elif defined(TARGET_X86_64) && !defined(USE_KQEMU)
#define TARGET_PHYS_ADDR_SPACE_BITS 40
#elif defined(TARGET_I386) && !defined(USE_KQEMU)
#define TARGET_PHYS_ADDR_SPACE_BITS 36
#else
/* Note: for compatibility with kqemu, we use 32 bits for x86_64 */
#define TARGET_PHYS_ADDR_SPACE_BITS 32
@ -88,7 +92,7 @@ spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE] __attribute__((aligned (32)));
uint8_t *code_gen_ptr;
int phys_ram_size;
ram_addr_t phys_ram_size;
int phys_ram_fd;
uint8_t *phys_ram_base;
uint8_t *phys_ram_dirty;
@ -113,7 +117,7 @@ typedef struct PageDesc {
typedef struct PhysPageDesc {
/* offset in host memory of the page + io_index in the low 12 bits */
uint32_t phys_offset;
ram_addr_t phys_offset;
} PhysPageDesc;
#define L2_BITS 10
@ -124,9 +128,14 @@ typedef struct PhysPageDesc {
*/
#define L1_BITS (TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS)
#else
#define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS)
#define L1_BITS (TARGET_PHYS_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS)
#endif
#undef L1_BITS
#undef L2_BITS
#define L1_BITS 13
#define L2_BITS 13
#define L1_SIZE (1 << L1_BITS)
#define L2_SIZE (1 << L2_BITS)
@ -234,7 +243,7 @@ static void page_init(void)
#endif
}
static inline PageDesc *page_find_alloc(unsigned int index)
static inline PageDesc *page_find_alloc(target_ulong index)
{
PageDesc **lp, *p;
@ -249,7 +258,7 @@ static inline PageDesc *page_find_alloc(unsigned int index)
return p + (index & (L2_SIZE - 1));
}
static inline PageDesc *page_find(unsigned int index)
static inline PageDesc *page_find(target_ulong index)
{
PageDesc *p;
@ -265,6 +274,7 @@ static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
PhysPageDesc *pd;
p = (void **)l1_phys_map;
#if 0
#if TARGET_PHYS_ADDR_SPACE_BITS > 32
#if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS)
@ -280,6 +290,7 @@ static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
memset(p, 0, sizeof(void *) * L1_SIZE);
*lp = p;
}
#endif
#endif
lp = p + ((index >> L2_BITS) & (L1_SIZE - 1));
pd = *lp;
@ -511,12 +522,12 @@ static inline void tb_reset_jump(TranslationBlock *tb, int n)
tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));
}
static inline void tb_phys_invalidate(TranslationBlock *tb, unsigned int page_addr)
static inline void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr)
{
CPUState *env;
PageDesc *p;
unsigned int h, n1;
target_ulong phys_pc;
target_phys_addr_t phys_pc;
TranslationBlock *tb1, *tb2;
/* remove the TB from the hash list */
@ -667,7 +678,7 @@ static void tb_gen_code(CPUState *env,
the same physical page. 'is_cpu_write_access' should be true if called
from a real cpu write access: the virtual CPU will exit the current
TB if code is modified inside this TB. */
void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
int is_cpu_write_access)
{
int n, current_tb_modified, current_tb_not_found, current_flags;
@ -780,7 +791,7 @@ void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
}
/* len must be <= 8 and start must be a multiple of len */
static inline void tb_invalidate_phys_page_fast(target_ulong start, int len)
static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len)
{
PageDesc *p;
int offset, b;
@ -809,7 +820,7 @@ static inline void tb_invalidate_phys_page_fast(target_ulong start, int len)
}
#if !defined(CONFIG_SOFTMMU)
static void tb_invalidate_phys_page(target_ulong addr,
static void tb_invalidate_phys_page(target_phys_addr_t addr,
unsigned long pc, void *puc)
{
int n, current_flags, current_tb_modified;
@ -1986,7 +1997,7 @@ static inline void tlb_set_dirty(CPUState *env,
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
int memory);
static void *subpage_init (target_phys_addr_t base, uint32_t *phys,
static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
int orig_memory);
#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
need_subpage) \
@ -2012,13 +2023,13 @@ static void *subpage_init (target_phys_addr_t base, uint32_t *phys,
page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
io memory page */
void cpu_register_physical_memory(target_phys_addr_t start_addr,
unsigned long size,
unsigned long phys_offset)
ram_addr_t size,
ram_addr_t phys_offset)
{
target_phys_addr_t addr, end_addr;
PhysPageDesc *p;
CPUState *env;
unsigned long orig_size = size;
ram_addr_t orig_size = size;
void *subpage;
size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
@ -2026,7 +2037,7 @@ void cpu_register_physical_memory(target_phys_addr_t start_addr,
for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
p = phys_page_find(addr >> TARGET_PAGE_BITS);
if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
unsigned long orig_memory = p->phys_offset;
ram_addr_t orig_memory = p->phys_offset;
target_phys_addr_t start_addr2, end_addr2;
int need_subpage = 0;
@ -2079,7 +2090,7 @@ void cpu_register_physical_memory(target_phys_addr_t start_addr,
}
/* XXX: temporary until new memory mapping API */
uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr)
ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr)
{
PhysPageDesc *p;
@ -2090,12 +2101,12 @@ uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr)
}
/* XXX: better than nothing */
ram_addr_t qemu_ram_alloc(unsigned int size)
ram_addr_t qemu_ram_alloc(ram_addr_t size)
{
ram_addr_t addr;
if ((phys_ram_alloc_offset + size) >= phys_ram_size) {
fprintf(stderr, "Not enough memory (requested_size = %u, max memory = %d)\n",
size, phys_ram_size);
fprintf(stderr, "Not enough memory (requested_size = %lu, max memory = %" PRIu64 ")\n",
size, (uint64_t)phys_ram_size);
abort();
}
addr = phys_ram_alloc_offset;
@ -2438,7 +2449,7 @@ static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
return 0;
}
static void *subpage_init (target_phys_addr_t base, uint32_t *phys,
static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
int orig_memory)
{
subpage_t *mmio;

2
hw/an5206.c
View File

@ -30,7 +30,7 @@ void DMA_run (void)
/* Board init. */
static void an5206_init(int ram_size, int vga_ram_size,
static void an5206_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

2
hw/boards.h
View File

@ -3,7 +3,7 @@
#ifndef HW_BOARDS_H
#define HW_BOARDS_H
typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
typedef void QEMUMachineInitFunc(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename,
const char *kernel_cmdline,

2
hw/dummy_m68k.c
View File

@ -14,7 +14,7 @@
/* Board init. */
static void dummy_m68k_init(int ram_size, int vga_ram_size,
static void dummy_m68k_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

2
hw/etraxfs.c
View File

@ -41,7 +41,7 @@ void etraxfs_timer_init(CPUState *env, qemu_irq *irqs,
void etraxfs_ser_init(CPUState *env, qemu_irq *irqs, target_phys_addr_t base);
static
void bareetraxfs_init (int ram_size, int vga_ram_size,
void bareetraxfs_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

4
hw/gumstix.c
View File

@ -41,7 +41,7 @@
static const int sector_len = 128 * 1024;
static void connex_init(int ram_size, int vga_ram_size,
static void connex_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -81,7 +81,7 @@ static void connex_init(int ram_size, int vga_ram_size,
pxa2xx_gpio_in_get(cpu->gpio)[36]);
}
static void verdex_init(int ram_size, int vga_ram_size,
static void verdex_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

2
hw/integratorcp.c
View File

@ -474,7 +474,7 @@ static struct arm_boot_info integrator_binfo = {
.board_id = 0x113,
};
static void integratorcp_init(int ram_size, int vga_ram_size,
static void integratorcp_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

4
hw/mainstone.c
View File

@ -64,7 +64,7 @@ static struct arm_boot_info mainstone_binfo = {
.ram_size = 0x04000000,
};
static void mainstone_common_init(int ram_size, int vga_ram_size,
static void mainstone_common_init(ram_addr_t ram_size, int vga_ram_size,
DisplayState *ds, const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, enum mainstone_model_e model, int arm_id)
@ -133,7 +133,7 @@ static void mainstone_common_init(int ram_size, int vga_ram_size,
arm_load_kernel(cpu->env, &mainstone_binfo);
}
static void mainstone_init(int ram_size, int vga_ram_size,
static void mainstone_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

2
hw/mcf5208.c
View File

@ -202,7 +202,7 @@ static void mcf5208_sys_init(qemu_irq *pic)
}
}
static void mcf5208evb_init(int ram_size, int vga_ram_size,
static void mcf5208evb_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

6
hw/mips_jazz.c
View File

@ -116,7 +116,7 @@ void espdma_memory_write(void *opaque, uint8_t *buf, int len)
#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
static
void mips_jazz_init (int ram_size, int vga_ram_size,
void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
DisplayState *ds, const char *cpu_model,
enum jazz_model_e jazz_model)
{
@ -256,7 +256,7 @@ void mips_jazz_init (int ram_size, int vga_ram_size,
}
static
void mips_magnum_init (int ram_size, int vga_ram_size,
void mips_magnum_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -265,7 +265,7 @@ void mips_magnum_init (int ram_size, int vga_ram_size,
}
static
void mips_pica61_init (int ram_size, int vga_ram_size,
void mips_pica61_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

2
hw/mips_malta.c
View File

@ -763,7 +763,7 @@ static void main_cpu_reset(void *opaque)
}
static
void mips_malta_init (int ram_size, int vga_ram_size,
void mips_malta_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

2
hw/mips_mipssim.c
View File

@ -106,7 +106,7 @@ static void main_cpu_reset(void *opaque)
}
static void
mips_mipssim_init (int ram_size, int vga_ram_size,
mips_mipssim_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

2
hw/mips_r4k.c
View File

@ -147,7 +147,7 @@ static void main_cpu_reset(void *opaque)
static const int sector_len = 32 * 1024;
static
void mips_r4k_init (int ram_size, int vga_ram_size,
void mips_r4k_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

2
hw/nseries.c
View File

@ -891,7 +891,7 @@ static struct arm_boot_info n800_binfo = {
.atag_board = n800_atag_setup,
};
static void n800_init(int ram_size, int vga_ram_size,
static void n800_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

2
hw/palm.c
View File

@ -192,7 +192,7 @@ static struct arm_boot_info palmte_binfo = {
.board_id = 0x331,
};
static void palmte_init(int ram_size, int vga_ram_size,
static void palmte_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

33
hw/pc.c
View File

@ -188,7 +188,8 @@ static int boot_device2nibble(char boot_device)
}
/* hd_table must contain 4 block drivers */
static void cmos_init(int ram_size, const char *boot_device, BlockDriverState **hd_table)
static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
const char *boot_device, BlockDriverState **hd_table)
{
RTCState *s = rtc_state;
int nbds, bds[3] = { 0, };
@ -211,6 +212,12 @@ static void cmos_init(int ram_size, const char *boot_device, BlockDriverState **
rtc_set_memory(s, 0x30, val);
rtc_set_memory(s, 0x31, val >> 8);
if (above_4g_mem_size) {
rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
}
if (ram_size > (16 * 1024 * 1024))
val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
else
@ -676,7 +683,7 @@ static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
}
/* PC hardware initialisation */
static void pc_init1(int ram_size, int vga_ram_size,
static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename,
@ -685,6 +692,7 @@ static void pc_init1(int ram_size, int vga_ram_size,
char buf[1024];
int ret, linux_boot, i;
ram_addr_t ram_addr, vga_ram_addr, bios_offset, vga_bios_offset;
ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
int bios_size, isa_bios_size, vga_bios_size;
PCIBus *pci_bus;
int piix3_devfn = -1;
@ -696,6 +704,13 @@ static void pc_init1(int ram_size, int vga_ram_size,
BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
BlockDriverState *fd[MAX_FD];
if (ram_size >= 0xe0000000 ) {
above_4g_mem_size = ram_size - 0xe0000000;
below_4g_mem_size = 0xe0000000;
} else {
below_4g_mem_size = ram_size;
}
linux_boot = (kernel_filename != NULL);
/* init CPUs */
@ -730,7 +745,13 @@ static void pc_init1(int ram_size, int vga_ram_size,
/* allocate RAM */
ram_addr = qemu_ram_alloc(ram_size);
cpu_register_physical_memory(0, ram_size, ram_addr);
cpu_register_physical_memory(0, below_4g_mem_size, ram_addr);
/* above 4giga memory allocation */
if (above_4g_mem_size > 0) {
cpu_register_physical_memory(0x100000000ULL, above_4g_mem_size,
ram_addr + below_4g_mem_size);
}
/* allocate VGA RAM */
vga_ram_addr = qemu_ram_alloc(vga_ram_size);
@ -950,7 +971,7 @@ static void pc_init1(int ram_size, int vga_ram_size,
}
floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
cmos_init(ram_size, boot_device, hd);
cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
if (pci_enabled && usb_enabled) {
usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
@ -990,7 +1011,7 @@ static void pc_init1(int ram_size, int vga_ram_size,
}
}
static void pc_init_pci(int ram_size, int vga_ram_size,
static void pc_init_pci(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename,
const char *kernel_cmdline,
@ -1002,7 +1023,7 @@ static void pc_init_pci(int ram_size, int vga_ram_size,
initrd_filename, 1, cpu_model);
}
static void pc_init_isa(int ram_size, int vga_ram_size,
static void pc_init_isa(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename,
const char *kernel_cmdline,

2
hw/piix_pci.c
View File

@ -55,7 +55,7 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
return (irq_num + slot_addend) & 3;
}
static uint32_t isa_page_descs[384 / 4];
static target_phys_addr_t isa_page_descs[384 / 4];
static uint8_t smm_enabled;
static int pci_irq_levels[4];

4
hw/ppc405_boards.c
View File

@ -177,7 +177,7 @@ static void ref405ep_fpga_init (uint32_t base)
}
}
static void ref405ep_init (int ram_size, int vga_ram_size,
static void ref405ep_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename,
const char *kernel_cmdline,
@ -504,7 +504,7 @@ static void taihu_cpld_init (uint32_t base)
}
}
static void taihu_405ep_init(int ram_size, int vga_ram_size,
static void taihu_405ep_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename,
const char *kernel_cmdline,

2
hw/ppc_chrp.c
View File

@ -57,7 +57,7 @@ static CPUReadMemoryFunc *unin_read[] = {
};
/* PowerPC Mac99 hardware initialisation */
static void ppc_core99_init (int ram_size, int vga_ram_size,
static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename,
const char *kernel_cmdline,

2
hw/ppc_oldworld.c
View File

@ -103,7 +103,7 @@ static int vga_osi_call (CPUState *env)
return 1; /* osi_call handled */
}
static void ppc_heathrow_init (int ram_size, int vga_ram_size,
static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename,
const char *kernel_cmdline,

2
hw/ppc_prep.c
View File

@ -535,7 +535,7 @@ CPUReadMemoryFunc *PPC_prep_io_read[] = {
#define NVRAM_SIZE 0x2000
/* PowerPC PREP hardware initialisation */
static void ppc_prep_init (int ram_size, int vga_ram_size,
static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename,
const char *kernel_cmdline,

2
hw/r2d.c
View File

@ -30,7 +30,7 @@
#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
#define SDRAM_SIZE 0x04000000
static void r2d_init(int ram_size, int vga_ram_size,
static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState * ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

2
hw/realview.c
View File

@ -23,7 +23,7 @@ static struct arm_boot_info realview_binfo = {
.board_id = 0x33b,
};
static void realview_init(int ram_size, int vga_ram_size,
static void realview_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

2
hw/shix.c
View File

@ -65,7 +65,7 @@ void vga_screen_dump(const char *filename)
/* XXXXX */
}
static void shix_init(int ram_size, int vga_ram_size,
static void shix_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState * ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

10
hw/spitz.c
View File

@ -1185,7 +1185,7 @@ static struct arm_boot_info spitz_binfo = {
.ram_size = 0x04000000,
};
static void spitz_common_init(int ram_size, int vga_ram_size,
static void spitz_common_init(ram_addr_t ram_size, int vga_ram_size,
DisplayState *ds, const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, enum spitz_model_e model, int arm_id)
@ -1245,7 +1245,7 @@ static void spitz_common_init(int ram_size, int vga_ram_size,
sl_bootparam_write(SL_PXA_PARAM_BASE - PXA2XX_SDRAM_BASE);
}
static void spitz_init(int ram_size, int vga_ram_size,
static void spitz_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -1254,7 +1254,7 @@ static void spitz_init(int ram_size, int vga_ram_size,
kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
}
static void borzoi_init(int ram_size, int vga_ram_size,
static void borzoi_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -1263,7 +1263,7 @@ static void borzoi_init(int ram_size, int vga_ram_size,
kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
}
static void akita_init(int ram_size, int vga_ram_size,
static void akita_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -1272,7 +1272,7 @@ static void akita_init(int ram_size, int vga_ram_size,
kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
}
static void terrier_init(int ram_size, int vga_ram_size,
static void terrier_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

4
hw/stellaris.c
View File

@ -1169,7 +1169,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
}
/* FIXME: Figure out how to generate these from stellaris_boards. */
static void lm3s811evb_init(int ram_size, int vga_ram_size,
static void lm3s811evb_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -1177,7 +1177,7 @@ static void lm3s811evb_init(int ram_size, int vga_ram_size,
stellaris_init(kernel_filename, cpu_model, ds, &stellaris_boards[0]);
}
static void lm3s6965evb_init(int ram_size, int vga_ram_size,
static void lm3s6965evb_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

14
hw/sun4m.c
View File

@ -1110,7 +1110,7 @@ static const struct hwdef hwdefs[] = {
};
/* SPARCstation 5 hardware initialisation */
static void ss5_init(int RAM_size, int vga_ram_size,
static void ss5_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -1120,7 +1120,7 @@ static void ss5_init(int RAM_size, int vga_ram_size,
}
/* SPARCstation 10 hardware initialisation */
static void ss10_init(int RAM_size, int vga_ram_size,
static void ss10_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -1130,7 +1130,7 @@ static void ss10_init(int RAM_size, int vga_ram_size,
}
/* SPARCserver 600MP hardware initialisation */
static void ss600mp_init(int RAM_size, int vga_ram_size,
static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -1140,7 +1140,7 @@ static void ss600mp_init(int RAM_size, int vga_ram_size,
}
/* SPARCstation 20 hardware initialisation */
static void ss20_init(int RAM_size, int vga_ram_size,
static void ss20_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -1150,7 +1150,7 @@ static void ss20_init(int RAM_size, int vga_ram_size,
}
/* SPARCstation 2 hardware initialisation */
static void ss2_init(int RAM_size, int vga_ram_size,
static void ss2_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -1480,7 +1480,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, int RAM_size,
}
/* SPARCserver 1000 hardware initialisation */
static void ss1000_init(int RAM_size, int vga_ram_size,
static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -1490,7 +1490,7 @@ static void ss1000_init(int RAM_size, int vga_ram_size,
}
/* SPARCcenter 2000 hardware initialisation */
static void ss2000_init(int RAM_size, int vga_ram_size,
static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

2
hw/sun4u.c
View File

@ -227,7 +227,7 @@ static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
static fdctrl_t *floppy_controller;
/* Sun4u hardware initialisation */
static void sun4u_init(int ram_size, int vga_ram_size,
static void sun4u_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_devices, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

6
hw/versatilepb.c
View File

@ -159,7 +159,7 @@ static qemu_irq *vpb_sic_init(uint32_t base, qemu_irq *parent, int irq)
static struct arm_boot_info versatile_binfo;
static void versatile_init(int ram_size, int vga_ram_size,
static void versatile_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model,
@ -293,7 +293,7 @@ static void versatile_init(int ram_size, int vga_ram_size,
arm_load_kernel(env, &versatile_binfo);
}
static void vpb_init(int ram_size, int vga_ram_size,
static void vpb_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -304,7 +304,7 @@ static void vpb_init(int ram_size, int vga_ram_size,
initrd_filename, cpu_model, 0x183);
}
static void vab_init(int ram_size, int vga_ram_size,
static void vab_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)

1
osdep.c
View File

@ -98,7 +98,6 @@ static void *kqemu_vmalloc(size_t size)
int64_t free_space;
int ram_mb;
extern int ram_size;
free_space = (int64_t)stfs.f_bavail * stfs.f_bsize;
if ((ram_size + 8192 * 1024) >= free_space) {
ram_mb = (ram_size / (1024 * 1024));

4
qemu-doc.texi
View File

@ -322,7 +322,9 @@ Disable boot signature checking for floppy disks in Bochs BIOS. It may
be needed to boot from old floppy disks.
@item -m @var{megs}
Set virtual RAM size to @var{megs} megabytes. Default is 128 MiB.
Set virtual RAM size to @var{megs} megabytes. Default is 128 MiB. Optionally,
a suffix of ``M'' or ``G'' can be used to signify a value in megabytes or
gigabytes respectively.
@item -smp @var{n}
Simulate an SMP system with @var{n} CPUs. On the PC target, up to 255

1
sysemu.h
View File

@ -73,7 +73,6 @@ int tap_win32_init(VLANState *vlan, const char *ifname);
/* SLIRP */
void do_info_slirp(void);
extern int ram_size;
extern int bios_size;
extern int cirrus_vga_enabled;
extern int vmsvga_enabled;

50
vl.c
View File

@ -142,8 +142,6 @@ int inet_aton(const char *cp, struct in_addr *ia);
//#define DEBUG_UNUSED_IOPORT
//#define DEBUG_IOPORT
#define PHYS_RAM_MAX_SIZE (2047 * 1024 * 1024)
#ifdef TARGET_PPC
#define DEFAULT_RAM_SIZE 144
#else
@ -175,7 +173,7 @@ int nographic;
int curses;
const char* keyboard_layout = NULL;
int64_t ticks_per_sec;
int ram_size;
ram_addr_t ram_size;
int pit_min_timer_count = 0;
int nb_nics;
NICInfo nd_table[MAX_NICS];
@ -6877,7 +6875,8 @@ static int ram_get_page(QEMUFile *f, uint8_t *buf, int len)
static int ram_load_v1(QEMUFile *f, void *opaque)
{
int i, ret;
int ret;
ram_addr_t i;
if (qemu_get_be32(f) != phys_ram_size)
return -EINVAL;
@ -7013,7 +7012,7 @@ static void ram_decompress_close(RamDecompressState *s)
static void ram_save(QEMUFile *f, void *opaque)
{
int i;
ram_addr_t i;
RamCompressState s1, *s = &s1;
uint8_t buf[10];
@ -7058,7 +7057,7 @@ static int ram_load(QEMUFile *f, void *opaque, int version_id)
{
RamDecompressState s1, *s = &s1;
uint8_t buf[10];
int i;
ram_addr_t i;
if (version_id == 1)
return ram_load_v1(f, opaque);
@ -7075,7 +7074,7 @@ static int ram_load(QEMUFile *f, void *opaque, int version_id)
}
if (buf[0] == 0) {
if (ram_decompress_buf(s, phys_ram_base + i, BDRV_HASH_BLOCK_SIZE) < 0) {
fprintf(stderr, "Error while reading ram block address=0x%08x", i);
fprintf(stderr, "Error while reading ram block address=0x%08" PRIx64, (uint64_t)i);
goto error;
}
} else
@ -8556,16 +8555,39 @@ int main(int argc, char **argv)
case QEMU_OPTION_h:
help(0);
break;
case QEMU_OPTION_m:
ram_size = atoi(optarg) * 1024 * 1024;
if (ram_size <= 0)
help(1);
if (ram_size > PHYS_RAM_MAX_SIZE) {
fprintf(stderr, "qemu: at most %d MB RAM can be simulated\n",
PHYS_RAM_MAX_SIZE / (1024 * 1024));
case QEMU_OPTION_m: {
uint64_t value;
char *ptr;
value = strtoul(optarg, &ptr, 10);
switch (*ptr) {
case 0: case 'M': case 'm':
value <<= 20;
break;
case 'G': case 'g':
value <<= 30;
break;
default:
fprintf(stderr, "qemu: invalid ram size: %s\n", optarg);
exit(1);
}
/* On 32-bit hosts, QEMU is limited by virtual address space */
if (value > (2047 << 20)
#ifndef USE_KQEMU
&& HOST_LONG_BITS == 32
#endif
) {
fprintf(stderr, "qemu: at most 2047 MB RAM can be simulated\n");
exit(1);
}
if (value != (uint64_t)(ram_addr_t)value) {
fprintf(stderr, "qemu: ram size too large\n");
exit(1);
}
ram_size = value;
break;
}
case QEMU_OPTION_d:
{
int mask;