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target/arm: Normalize aarch64 gdbstub get/set function names

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Make the form of the function names between fp and sve the same:
  - arm_gdb_*_svereg -> aarch64_gdb_*_sve_reg.
  - aarch64_fpu_gdb_*_reg -> aarch64_gdb_*_fpu_reg.

Reviewed-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2023-02-27 11:33:16 -10:00 committed by Peter Maydell
parent f003dd8d81
commit 963a6b91c2
3 changed files with 13 additions and 12 deletions
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9
target/arm/gdbstub.c
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@ -466,12 +466,13 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
*/ */
#ifdef TARGET_AARCH64 #ifdef TARGET_AARCH64
if (isar_feature_aa64_sve(&cpu->isar)) { if (isar_feature_aa64_sve(&cpu->isar)) {
gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg, int nreg = arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs);
arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs), gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg,
aarch64_gdb_set_sve_reg, nreg,
"sve-registers.xml", 0); "sve-registers.xml", 0);
} else { } else {
gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg,
aarch64_fpu_gdb_set_reg, aarch64_gdb_set_fpu_reg,
34, "aarch64-fpu.xml", 0); 34, "aarch64-fpu.xml", 0);
} }
#endif #endif

8
target/arm/gdbstub64.c
View File

@ -72,7 +72,7 @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
return 0; return 0;
} }
int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg)
{ {
switch (reg) { switch (reg) {
case 0 ... 31: case 0 ... 31:
@ -92,7 +92,7 @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
} }
} }
int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg)
{ {
switch (reg) { switch (reg) {
case 0 ... 31: case 0 ... 31:
@ -116,7 +116,7 @@ int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
} }
} }
int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg)
{ {
ARMCPU *cpu = env_archcpu(env); ARMCPU *cpu = env_archcpu(env);
@ -164,7 +164,7 @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
return 0; return 0;
} }
int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg) int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
{ {
ARMCPU *cpu = env_archcpu(env); ARMCPU *cpu = env_archcpu(env);

8
target/arm/internals.h
View File

@ -1344,10 +1344,10 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
} }
#ifdef TARGET_AARCH64 #ifdef TARGET_AARCH64
int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg); int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);