sparc64: fix loosing interrupts
- clear interrupts only on writing to the interrupt clear registers - don't overwrite a currently active interrupt request - use the correct addresses for the interrupt clear registers (section 19.3.3.3 of the UltraSPARC™-IIi User’s Manual) Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Artyom Tarasenko
Blue Swirl
parent
852e82f303
commit
9625036d14
@ -2,6 +2,7 @@
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* QEMU Ultrasparc APB PCI host
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*
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* Copyright (c) 2006 Fabrice Bellard
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* Copyright (c) 2012,2013 Artyom Tarasenko
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@ -67,6 +68,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
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#define RESET_WMASK 0x60000000
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#define MAX_IVEC 0x40
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#define NO_IRQ_REQUEST (MAX_IVEC + 1)
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typedef struct APBState {
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SysBusDevice busdev;
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@ -75,17 +77,64 @@ typedef struct APBState {
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MemoryRegion pci_config;
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MemoryRegion pci_mmio;
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MemoryRegion pci_ioport;
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uint64_t pci_irq_in;
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uint32_t iommu[4];
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uint32_t pci_control[16];
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uint32_t pci_irq_map[8];
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uint32_t obio_irq_map[32];
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qemu_irq *pbm_irqs;
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qemu_irq *ivec_irqs;
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unsigned int irq_request;
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uint32_t reset_control;
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unsigned int nr_resets;
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} APBState;
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static void pci_apb_set_irq(void *opaque, int irq_num, int level);
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static inline void pbm_set_request(APBState *s, unsigned int irq_num)
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{
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APB_DPRINTF("%s: request irq %d\n", __func__, irq_num);
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s->irq_request = irq_num;
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qemu_set_irq(s->ivec_irqs[irq_num], 1);
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}
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static inline void pbm_check_irqs(APBState *s)
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{
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unsigned int i;
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/* Previous request is not acknowledged, resubmit */
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if (s->irq_request != NO_IRQ_REQUEST) {
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pbm_set_request(s, s->irq_request);
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return;
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}
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/* no request pending */
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if (s->pci_irq_in == 0ULL) {
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return;
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}
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for (i = 0; i < 32; i++) {
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if (s->pci_irq_in & (1ULL << i)) {
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if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) {
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pbm_set_request(s, i);
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return;
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}
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}
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}
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for (i = 32; i < 64; i++) {
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if (s->pci_irq_in & (1ULL << i)) {
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if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) {
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pbm_set_request(s, i);
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break;
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}
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}
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}
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}
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static inline void pbm_clear_request(APBState *s, unsigned int irq_num)
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{
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APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
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qemu_set_irq(s->ivec_irqs[irq_num], 0);
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s->irq_request = NO_IRQ_REQUEST;
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}
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static void apb_config_writel (void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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@ -105,24 +154,43 @@ static void apb_config_writel (void *opaque, hwaddr addr,
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break;
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case 0xc00 ... 0xc3f: /* PCI interrupt control */
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if (addr & 4) {
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s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK;
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s->pci_irq_map[(addr & 0x3f) >> 3] |= val & ~PBM_PCI_IMR_MASK;
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unsigned int ino = (addr & 0x3f) >> 3;
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s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK;
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s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
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if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) {
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pbm_clear_request(s, ino);
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}
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pbm_check_irqs(s);
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}
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break;
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case 0x1000 ... 0x1080: /* OBIO interrupt control */
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if (addr & 4) {
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s->obio_irq_map[(addr & 0xff) >> 3] &= PBM_PCI_IMR_MASK;
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s->obio_irq_map[(addr & 0xff) >> 3] |= val & ~PBM_PCI_IMR_MASK;
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unsigned int ino = ((addr & 0xff) >> 3);
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s->obio_irq_map[ino] &= PBM_PCI_IMR_MASK;
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s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
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if ((s->irq_request == (ino | 0x20))
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&& !(val & ~PBM_PCI_IMR_MASK)) {
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pbm_clear_request(s, ino | 0x20);
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}
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pbm_check_irqs(s);
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}
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break;
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case 0x1400 ... 0x143f: /* PCI interrupt clear */
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case 0x1400 ... 0x14ff: /* PCI interrupt clear */
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if (addr & 4) {
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pci_apb_set_irq(s, (addr & 0x3f) >> 3, 0);
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unsigned int ino = (addr & 0xff) >> 5;
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if ((s->irq_request / 4) == ino) {
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pbm_clear_request(s, s->irq_request);
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pbm_check_irqs(s);
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}
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}
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break;
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case 0x1800 ... 0x1860: /* OBIO interrupt clear */
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if (addr & 4) {
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pci_apb_set_irq(s, 0x20 | ((addr & 0xff) >> 3), 0);
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unsigned int ino = ((addr & 0xff) >> 3) | 0x20;
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if (s->irq_request == ino) {
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pbm_clear_request(s, ino);
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pbm_check_irqs(s);
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}
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}
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break;
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case 0x2000 ... 0x202f: /* PCI control */
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@ -304,23 +372,28 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
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{
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APBState *s = opaque;
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APB_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level);
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/* PCI IRQ map onto the first 32 INO. */
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if (irq_num < 32) {
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if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
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APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
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qemu_set_irq(s->ivec_irqs[irq_num], level);
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if (level) {
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s->pci_irq_in |= 1ULL << irq_num;
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if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
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pbm_set_request(s, irq_num);
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}
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} else {
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APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
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qemu_irq_lower(s->ivec_irqs[irq_num]);
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s->pci_irq_in &= ~(1ULL << irq_num);
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}
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} else {
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/* OBIO IRQ map onto the next 16 INO. */
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if (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED) {
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/* OBIO IRQ map onto the next 32 INO. */
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if (level) {
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APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
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qemu_set_irq(s->ivec_irqs[irq_num], level);
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s->pci_irq_in |= 1ULL << irq_num;
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if ((s->irq_request == NO_IRQ_REQUEST)
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&& (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) {
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pbm_set_request(s, irq_num);
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}
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} else {
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APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
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qemu_irq_lower(s->ivec_irqs[irq_num]);
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s->pci_irq_in &= ~(1ULL << irq_num);
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}
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}
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}
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@ -420,6 +493,9 @@ static void pci_pbm_reset(DeviceState *d)
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s->obio_irq_map[i] &= PBM_PCI_IMR_MASK;
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}
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s->irq_request = NO_IRQ_REQUEST;
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s->pci_irq_in = 0ULL;
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if (s->nr_resets++ == 0) {
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/* Power on reset */
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s->reset_control = POR;
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@ -445,6 +521,8 @@ static int pci_pbm_init_device(SysBusDevice *dev)
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s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;
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}
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s->pbm_irqs = qemu_allocate_irqs(pci_apb_set_irq, s, MAX_IVEC);
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s->irq_request = NO_IRQ_REQUEST;
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s->pci_irq_in = 0ULL;
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/* apb_config */
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memory_region_init_io(&s->apb_config, &apb_config_ops, s, "apb-config",
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