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target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions

Browse Source 
Signed-off-by: Song Gao <gaosong@loongson.cn>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230822032724.1353391-12-gaosong@loongson.cn>
Message-Id: <20230822071959.35620-6-philmd@linaro.org>
This commit is contained in:
Song Gao 2023-08-22 09:19:55 +02:00
parent 3055122ff6
commit 95e2ca2407
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
7 changed files with 159 additions and 86 deletions
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96
target/loongarch/insn_trans/trans_farith.c.inc
View File

@ -67,6 +67,10 @@ static bool trans_fcopysign_s(DisasContext *ctx, arg_fcopysign_s *a)
TCGv src1 = get_fpr(ctx, a->fk);
TCGv src2 = get_fpr(ctx, a->fj);
if (!avail_FP_SP(ctx)) {
return false;
}
CHECK_FPE;
tcg_gen_deposit_i64(dest, src1, src2, 0, 31);
@ -81,6 +85,10 @@ static bool trans_fcopysign_d(DisasContext *ctx, arg_fcopysign_d *a)
TCGv src1 = get_fpr(ctx, a->fk);
TCGv src2 = get_fpr(ctx, a->fj);
if (!avail_FP_DP(ctx)) {
return false;
}
CHECK_FPE;
tcg_gen_deposit_i64(dest, src1, src2, 0, 63);
@ -94,6 +102,10 @@ static bool trans_fabs_s(DisasContext *ctx, arg_fabs_s *a)
TCGv dest = get_fpr(ctx, a->fd);
TCGv src = get_fpr(ctx, a->fj);
if (!avail_FP_SP(ctx)) {
return false;
}
CHECK_FPE;
tcg_gen_andi_i64(dest, src, MAKE_64BIT_MASK(0, 31));
@ -108,6 +120,10 @@ static bool trans_fabs_d(DisasContext *ctx, arg_fabs_d *a)
TCGv dest = get_fpr(ctx, a->fd);
TCGv src = get_fpr(ctx, a->fj);
if (!avail_FP_DP(ctx)) {
return false;
}
CHECK_FPE;
tcg_gen_andi_i64(dest, src, MAKE_64BIT_MASK(0, 63));
@ -121,6 +137,10 @@ static bool trans_fneg_s(DisasContext *ctx, arg_fneg_s *a)
TCGv dest = get_fpr(ctx, a->fd);
TCGv src = get_fpr(ctx, a->fj);
if (!avail_FP_SP(ctx)) {
return false;
}
CHECK_FPE;
tcg_gen_xori_i64(dest, src, 0x80000000);
@ -135,6 +155,10 @@ static bool trans_fneg_d(DisasContext *ctx, arg_fneg_d *a)
TCGv dest = get_fpr(ctx, a->fd);
TCGv src = get_fpr(ctx, a->fj);
if (!avail_FP_DP(ctx)) {
return false;
}
CHECK_FPE;
tcg_gen_xori_i64(dest, src, 0x8000000000000000LL);
@ -143,41 +167,41 @@ static bool trans_fneg_d(DisasContext *ctx, arg_fneg_d *a)
return true;
}
TRANS(fadd_s, ALL, gen_fff, gen_helper_fadd_s)
TRANS(fadd_d, ALL, gen_fff, gen_helper_fadd_d)
TRANS(fsub_s, ALL, gen_fff, gen_helper_fsub_s)
TRANS(fsub_d, ALL, gen_fff, gen_helper_fsub_d)
TRANS(fmul_s, ALL, gen_fff, gen_helper_fmul_s)
TRANS(fmul_d, ALL, gen_fff, gen_helper_fmul_d)
TRANS(fdiv_s, ALL, gen_fff, gen_helper_fdiv_s)
TRANS(fdiv_d, ALL, gen_fff, gen_helper_fdiv_d)
TRANS(fmax_s, ALL, gen_fff, gen_helper_fmax_s)
TRANS(fmax_d, ALL, gen_fff, gen_helper_fmax_d)
TRANS(fmin_s, ALL, gen_fff, gen_helper_fmin_s)
TRANS(fmin_d, ALL, gen_fff, gen_helper_fmin_d)
TRANS(fmaxa_s, ALL, gen_fff, gen_helper_fmaxa_s)
TRANS(fmaxa_d, ALL, gen_fff, gen_helper_fmaxa_d)
TRANS(fmina_s, ALL, gen_fff, gen_helper_fmina_s)
TRANS(fmina_d, ALL, gen_fff, gen_helper_fmina_d)
TRANS(fscaleb_s, ALL, gen_fff, gen_helper_fscaleb_s)
TRANS(fscaleb_d, ALL, gen_fff, gen_helper_fscaleb_d)
TRANS(fsqrt_s, ALL, gen_ff, gen_helper_fsqrt_s)
TRANS(fsqrt_d, ALL, gen_ff, gen_helper_fsqrt_d)
TRANS(frecip_s, ALL, gen_ff, gen_helper_frecip_s)
TRANS(frecip_d, ALL, gen_ff, gen_helper_frecip_d)
TRANS(frsqrt_s, ALL, gen_ff, gen_helper_frsqrt_s)
TRANS(frsqrt_d, ALL, gen_ff, gen_helper_frsqrt_d)
TRANS(flogb_s, ALL, gen_ff, gen_helper_flogb_s)
TRANS(flogb_d, ALL, gen_ff, gen_helper_flogb_d)
TRANS(fclass_s, ALL, gen_ff, gen_helper_fclass_s)
TRANS(fclass_d, ALL, gen_ff, gen_helper_fclass_d)
TRANS(fmadd_s, ALL, gen_muladd, gen_helper_fmuladd_s, 0)
TRANS(fmadd_d, ALL, gen_muladd, gen_helper_fmuladd_d, 0)
TRANS(fmsub_s, ALL, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_c)
TRANS(fmsub_d, ALL, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_c)
TRANS(fnmadd_s, ALL, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_result)
TRANS(fnmadd_d, ALL, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_result)
TRANS(fnmsub_s, ALL, gen_muladd, gen_helper_fmuladd_s,
TRANS(fadd_s, FP_SP, gen_fff, gen_helper_fadd_s)
TRANS(fadd_d, FP_DP, gen_fff, gen_helper_fadd_d)
TRANS(fsub_s, FP_SP, gen_fff, gen_helper_fsub_s)
TRANS(fsub_d, FP_DP, gen_fff, gen_helper_fsub_d)
TRANS(fmul_s, FP_SP, gen_fff, gen_helper_fmul_s)
TRANS(fmul_d, FP_DP, gen_fff, gen_helper_fmul_d)
TRANS(fdiv_s, FP_SP, gen_fff, gen_helper_fdiv_s)
TRANS(fdiv_d, FP_DP, gen_fff, gen_helper_fdiv_d)
TRANS(fmax_s, FP_SP, gen_fff, gen_helper_fmax_s)
TRANS(fmax_d, FP_DP, gen_fff, gen_helper_fmax_d)
TRANS(fmin_s, FP_SP, gen_fff, gen_helper_fmin_s)
TRANS(fmin_d, FP_DP, gen_fff, gen_helper_fmin_d)
TRANS(fmaxa_s, FP_SP, gen_fff, gen_helper_fmaxa_s)
TRANS(fmaxa_d, FP_DP, gen_fff, gen_helper_fmaxa_d)
TRANS(fmina_s, FP_SP, gen_fff, gen_helper_fmina_s)
TRANS(fmina_d, FP_DP, gen_fff, gen_helper_fmina_d)
TRANS(fscaleb_s, FP_SP, gen_fff, gen_helper_fscaleb_s)
TRANS(fscaleb_d, FP_DP, gen_fff, gen_helper_fscaleb_d)
TRANS(fsqrt_s, FP_SP, gen_ff, gen_helper_fsqrt_s)
TRANS(fsqrt_d, FP_DP, gen_ff, gen_helper_fsqrt_d)
TRANS(frecip_s, FP_SP, gen_ff, gen_helper_frecip_s)
TRANS(frecip_d, FP_DP, gen_ff, gen_helper_frecip_d)
TRANS(frsqrt_s, FP_SP, gen_ff, gen_helper_frsqrt_s)
TRANS(frsqrt_d, FP_DP, gen_ff, gen_helper_frsqrt_d)
TRANS(flogb_s, FP_SP, gen_ff, gen_helper_flogb_s)
TRANS(flogb_d, FP_DP, gen_ff, gen_helper_flogb_d)
TRANS(fclass_s, FP_SP, gen_ff, gen_helper_fclass_s)
TRANS(fclass_d, FP_DP, gen_ff, gen_helper_fclass_d)
TRANS(fmadd_s, FP_SP, gen_muladd, gen_helper_fmuladd_s, 0)
TRANS(fmadd_d, FP_DP, gen_muladd, gen_helper_fmuladd_d, 0)
TRANS(fmsub_s, FP_SP, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_c)
TRANS(fmsub_d, FP_DP, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_c)
TRANS(fnmadd_s, FP_SP, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_result)
TRANS(fnmadd_d, FP_DP, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_result)
TRANS(fnmsub_s, FP_SP, gen_muladd, gen_helper_fmuladd_s,
float_muladd_negate_c | float_muladd_negate_result)
TRANS(fnmsub_d, ALL, gen_muladd, gen_helper_fmuladd_d,
TRANS(fnmsub_d, FP_DP, gen_muladd, gen_helper_fmuladd_d,
float_muladd_negate_c | float_muladd_negate_result)

8
target/loongarch/insn_trans/trans_fcmp.c.inc
View File

@ -29,6 +29,10 @@ static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a)
uint32_t flags;
void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);
if (!avail_FP_SP(ctx)) {
return false;
}
CHECK_FPE;
var = tcg_temp_new();
@ -49,6 +53,10 @@ static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp_cond_d *a)
uint32_t flags;
void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);
if (!avail_FP_DP(ctx)) {
return false;
}
CHECK_FPE;
var = tcg_temp_new();

56
target/loongarch/insn_trans/trans_fcnv.c.inc
View File

@ -3,31 +3,31 @@
* Copyright (c) 2021 Loongson Technology Corporation Limited
*/
TRANS(fcvt_s_d, ALL, gen_ff, gen_helper_fcvt_s_d)
TRANS(fcvt_d_s, ALL, gen_ff, gen_helper_fcvt_d_s)
TRANS(ftintrm_w_s, ALL, gen_ff, gen_helper_ftintrm_w_s)
TRANS(ftintrm_w_d, ALL, gen_ff, gen_helper_ftintrm_w_d)
TRANS(ftintrm_l_s, ALL, gen_ff, gen_helper_ftintrm_l_s)
TRANS(ftintrm_l_d, ALL, gen_ff, gen_helper_ftintrm_l_d)
TRANS(ftintrp_w_s, ALL, gen_ff, gen_helper_ftintrp_w_s)
TRANS(ftintrp_w_d, ALL, gen_ff, gen_helper_ftintrp_w_d)
TRANS(ftintrp_l_s, ALL, gen_ff, gen_helper_ftintrp_l_s)
TRANS(ftintrp_l_d, ALL, gen_ff, gen_helper_ftintrp_l_d)
TRANS(ftintrz_w_s, ALL, gen_ff, gen_helper_ftintrz_w_s)
TRANS(ftintrz_w_d, ALL, gen_ff, gen_helper_ftintrz_w_d)
TRANS(ftintrz_l_s, ALL, gen_ff, gen_helper_ftintrz_l_s)
TRANS(ftintrz_l_d, ALL, gen_ff, gen_helper_ftintrz_l_d)
TRANS(ftintrne_w_s, ALL, gen_ff, gen_helper_ftintrne_w_s)
TRANS(ftintrne_w_d, ALL, gen_ff, gen_helper_ftintrne_w_d)
TRANS(ftintrne_l_s, ALL, gen_ff, gen_helper_ftintrne_l_s)
TRANS(ftintrne_l_d, ALL, gen_ff, gen_helper_ftintrne_l_d)
TRANS(ftint_w_s, ALL, gen_ff, gen_helper_ftint_w_s)
TRANS(ftint_w_d, ALL, gen_ff, gen_helper_ftint_w_d)
TRANS(ftint_l_s, ALL, gen_ff, gen_helper_ftint_l_s)
TRANS(ftint_l_d, ALL, gen_ff, gen_helper_ftint_l_d)
TRANS(ffint_s_w, ALL, gen_ff, gen_helper_ffint_s_w)
TRANS(ffint_s_l, ALL, gen_ff, gen_helper_ffint_s_l)
TRANS(ffint_d_w, ALL, gen_ff, gen_helper_ffint_d_w)
TRANS(ffint_d_l, ALL, gen_ff, gen_helper_ffint_d_l)
TRANS(frint_s, ALL, gen_ff, gen_helper_frint_s)
TRANS(frint_d, ALL, gen_ff, gen_helper_frint_d)
TRANS(fcvt_s_d, FP_DP, gen_ff, gen_helper_fcvt_s_d)
TRANS(fcvt_d_s, FP_DP, gen_ff, gen_helper_fcvt_d_s)
TRANS(ftintrm_w_s, FP_SP, gen_ff, gen_helper_ftintrm_w_s)
TRANS(ftintrm_w_d, FP_DP, gen_ff, gen_helper_ftintrm_w_d)
TRANS(ftintrm_l_s, FP_SP, gen_ff, gen_helper_ftintrm_l_s)
TRANS(ftintrm_l_d, FP_DP, gen_ff, gen_helper_ftintrm_l_d)
TRANS(ftintrp_w_s, FP_SP, gen_ff, gen_helper_ftintrp_w_s)
TRANS(ftintrp_w_d, FP_DP, gen_ff, gen_helper_ftintrp_w_d)
TRANS(ftintrp_l_s, FP_SP, gen_ff, gen_helper_ftintrp_l_s)
TRANS(ftintrp_l_d, FP_DP, gen_ff, gen_helper_ftintrp_l_d)
TRANS(ftintrz_w_s, FP_SP, gen_ff, gen_helper_ftintrz_w_s)
TRANS(ftintrz_w_d, FP_DP, gen_ff, gen_helper_ftintrz_w_d)
TRANS(ftintrz_l_s, FP_SP, gen_ff, gen_helper_ftintrz_l_s)
TRANS(ftintrz_l_d, FP_DP, gen_ff, gen_helper_ftintrz_l_d)
TRANS(ftintrne_w_s, FP_SP, gen_ff, gen_helper_ftintrne_w_s)
TRANS(ftintrne_w_d, FP_DP, gen_ff, gen_helper_ftintrne_w_d)
TRANS(ftintrne_l_s, FP_SP, gen_ff, gen_helper_ftintrne_l_s)
TRANS(ftintrne_l_d, FP_DP, gen_ff, gen_helper_ftintrne_l_d)
TRANS(ftint_w_s, FP_SP, gen_ff, gen_helper_ftint_w_s)
TRANS(ftint_w_d, FP_DP, gen_ff, gen_helper_ftint_w_d)
TRANS(ftint_l_s, FP_SP, gen_ff, gen_helper_ftint_l_s)
TRANS(ftint_l_d, FP_DP, gen_ff, gen_helper_ftint_l_d)
TRANS(ffint_s_w, FP_SP, gen_ff, gen_helper_ffint_s_w)
TRANS(ffint_s_l, FP_SP, gen_ff, gen_helper_ffint_s_l)
TRANS(ffint_d_w, FP_DP, gen_ff, gen_helper_ffint_d_w)
TRANS(ffint_d_l, FP_DP, gen_ff, gen_helper_ffint_d_l)
TRANS(frint_s, FP_SP, gen_ff, gen_helper_frint_s)
TRANS(frint_d, FP_DP, gen_ff, gen_helper_frint_d)

32
target/loongarch/insn_trans/trans_fmemory.c.inc
View File

@ -140,19 +140,19 @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a, MemOp mop)
return true;
}
TRANS(fld_s, ALL, gen_fload_i, MO_TEUL)
TRANS(fst_s, ALL, gen_fstore_i, MO_TEUL)
TRANS(fld_d, ALL, gen_fload_i, MO_TEUQ)
TRANS(fst_d, ALL, gen_fstore_i, MO_TEUQ)
TRANS(fldx_s, ALL, gen_floadx, MO_TEUL)
TRANS(fldx_d, ALL, gen_floadx, MO_TEUQ)
TRANS(fstx_s, ALL, gen_fstorex, MO_TEUL)
TRANS(fstx_d, ALL, gen_fstorex, MO_TEUQ)
TRANS(fldgt_s, ALL, gen_fload_gt, MO_TEUL)
TRANS(fldgt_d, ALL, gen_fload_gt, MO_TEUQ)
TRANS(fldle_s, ALL, gen_fload_le, MO_TEUL)
TRANS(fldle_d, ALL, gen_fload_le, MO_TEUQ)
TRANS(fstgt_s, ALL, gen_fstore_gt, MO_TEUL)
TRANS(fstgt_d, ALL, gen_fstore_gt, MO_TEUQ)
TRANS(fstle_s, ALL, gen_fstore_le, MO_TEUL)
TRANS(fstle_d, ALL, gen_fstore_le, MO_TEUQ)
TRANS(fld_s, FP_SP, gen_fload_i, MO_TEUL)
TRANS(fst_s, FP_SP, gen_fstore_i, MO_TEUL)
TRANS(fld_d, FP_DP, gen_fload_i, MO_TEUQ)
TRANS(fst_d, FP_DP, gen_fstore_i, MO_TEUQ)
TRANS(fldx_s, FP_SP, gen_floadx, MO_TEUL)
TRANS(fldx_d, FP_DP, gen_floadx, MO_TEUQ)
TRANS(fstx_s, FP_SP, gen_fstorex, MO_TEUL)
TRANS(fstx_d, FP_DP, gen_fstorex, MO_TEUQ)
TRANS(fldgt_s, FP_SP, gen_fload_gt, MO_TEUL)
TRANS(fldgt_d, FP_DP, gen_fload_gt, MO_TEUQ)
TRANS(fldle_s, FP_SP, gen_fload_le, MO_TEUL)
TRANS(fldle_d, FP_DP, gen_fload_le, MO_TEUQ)
TRANS(fstgt_s, FP_SP, gen_fstore_gt, MO_TEUL)
TRANS(fstgt_d, FP_DP, gen_fstore_gt, MO_TEUQ)
TRANS(fstle_s, FP_SP, gen_fstore_le, MO_TEUL)
TRANS(fstle_d, FP_DP, gen_fstore_le, MO_TEUQ)

48
target/loongarch/insn_trans/trans_fmov.c.inc
View File

@ -15,6 +15,10 @@ static bool trans_fsel(DisasContext *ctx, arg_fsel *a)
TCGv src2 = get_fpr(ctx, a->fk);
TCGv cond;
if (!avail_FP(ctx)) {
return false;
}
CHECK_FPE;
cond = tcg_temp_new();
@ -48,6 +52,10 @@ static bool gen_r2f(DisasContext *ctx, arg_fr *a,
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
TCGv dest = get_fpr(ctx, a->fd);
if (!avail_FP(ctx)) {
return false;
}
CHECK_FPE;
func(dest, src);
@ -62,6 +70,10 @@ static bool gen_f2r(DisasContext *ctx, arg_rf *a,
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
TCGv src = get_fpr(ctx, a->fj);
if (!avail_FP(ctx)) {
return false;
}
CHECK_FPE;
func(dest, src);
@ -75,6 +87,10 @@ static bool trans_movgr2fcsr(DisasContext *ctx, arg_movgr2fcsr *a)
uint32_t mask = fcsr_mask[a->fcsrd];
TCGv Rj = gpr_src(ctx, a->rj, EXT_NONE);
if (!avail_FP(ctx)) {
return false;
}
CHECK_FPE;
if (mask == UINT32_MAX) {
@ -105,6 +121,10 @@ static bool trans_movfcsr2gr(DisasContext *ctx, arg_movfcsr2gr *a)
{
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
if (!avail_FP(ctx)) {
return false;
}
CHECK_FPE;
tcg_gen_ld32u_i64(dest, cpu_env, offsetof(CPULoongArchState, fcsr0));
@ -134,6 +154,10 @@ static bool trans_movfr2cf(DisasContext *ctx, arg_movfr2cf *a)
TCGv t0;
TCGv src = get_fpr(ctx, a->fj);
if (!avail_FP(ctx)) {
return false;
}
CHECK_FPE;
t0 = tcg_temp_new();
@ -147,6 +171,10 @@ static bool trans_movcf2fr(DisasContext *ctx, arg_movcf2fr *a)
{
TCGv dest = get_fpr(ctx, a->fd);
if (!avail_FP(ctx)) {
return false;
}
CHECK_FPE;
tcg_gen_ld8u_tl(dest, cpu_env,
@ -160,6 +188,10 @@ static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf *a)
{
TCGv t0;
if (!avail_FP(ctx)) {
return false;
}
CHECK_FPE;
t0 = tcg_temp_new();
@ -171,6 +203,10 @@ static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf *a)
static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a)
{
if (!avail_FP(ctx)) {
return false;
}
CHECK_FPE;
tcg_gen_ld8u_tl(gpr_dst(ctx, a->rd, EXT_NONE), cpu_env,
@ -178,11 +214,11 @@ static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a)
return true;
}
TRANS(fmov_s, ALL, gen_f2f, tcg_gen_mov_tl, true)
TRANS(fmov_d, ALL, gen_f2f, tcg_gen_mov_tl, false)
TRANS(movgr2fr_w, ALL, gen_r2f, gen_movgr2fr_w)
TRANS(fmov_s, FP_SP, gen_f2f, tcg_gen_mov_tl, true)
TRANS(fmov_d, FP_DP, gen_f2f, tcg_gen_mov_tl, false)
TRANS(movgr2fr_w, FP_SP, gen_r2f, gen_movgr2fr_w)
TRANS(movgr2fr_d, 64, gen_r2f, tcg_gen_mov_tl)
TRANS(movgr2frh_w, ALL, gen_r2f, gen_movgr2frh_w)
TRANS(movfr2gr_s, ALL, gen_f2r, tcg_gen_ext32s_tl)
TRANS(movgr2frh_w, FP_DP, gen_r2f, gen_movgr2frh_w)
TRANS(movfr2gr_s, FP_SP, gen_f2r, tcg_gen_ext32s_tl)
TRANS(movfr2gr_d, 64, gen_f2r, tcg_gen_mov_tl)
TRANS(movfrh2gr_s, ALL, gen_f2r, gen_movfrh2gr_s)
TRANS(movfrh2gr_s, FP_DP, gen_f2r, gen_movfrh2gr_s)

1
target/loongarch/translate.c
View File

@ -129,6 +129,7 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,
ctx->zero = tcg_constant_tl(0);
ctx->cpucfg1 = env->cpucfg[1];
ctx->cpucfg2 = env->cpucfg[2];
}
static void loongarch_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)

4
target/loongarch/translate.h
View File

@ -17,6 +17,9 @@
#define avail_ALL(C) true
#define avail_64(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, ARCH) == \
CPUCFG1_ARCH_LA64)
#define avail_FP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP))
#define avail_FP_SP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_SP))
#define avail_FP_DP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_DP))
/*
* If an operation is being performed on less than TARGET_LONG_BITS,
@ -40,6 +43,7 @@ typedef struct DisasContext {
bool la64; /* LoongArch64 mode */
bool va32; /* 32-bit virtual address */
uint32_t cpucfg1;
uint32_t cpucfg2;
} DisasContext;
void generate_exception(DisasContext *ctx, int excp);