target/mips: Create mips_io_recompile_replay_branch
Move the code from accel/tcg/translate-all.c to target/mips/cpu.c. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210208233906.479571-4-richard.henderson@linaro.org> Message-Id: <20210213130325.14781-13-alex.bennee@linaro.org>
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@ -2418,7 +2418,7 @@ void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr)
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*/
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void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
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{
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#if defined(TARGET_MIPS) || defined(TARGET_SH4)
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#if defined(TARGET_SH4)
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CPUArchState *env = cpu->env_ptr;
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#endif
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TranslationBlock *tb;
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@ -2444,15 +2444,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
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cpu_neg(cpu)->icount_decr.u16.low++;
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n = 2;
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}
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#if defined(TARGET_MIPS)
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if ((env->hflags & MIPS_HFLAG_BMASK) != 0
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&& env->active_tc.PC != tb->pc) {
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env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
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cpu_neg(cpu)->icount_decr.u16.low++;
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env->hflags &= ~MIPS_HFLAG_BMASK;
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n = 2;
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}
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#elif defined(TARGET_SH4)
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#if defined(TARGET_SH4)
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if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
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&& env->pc != tb->pc) {
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env->pc -= 2;
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@ -268,6 +268,23 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs,
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env->hflags &= ~MIPS_HFLAG_BMASK;
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env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
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}
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# ifndef CONFIG_USER_ONLY
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static bool mips_io_recompile_replay_branch(CPUState *cs,
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const TranslationBlock *tb)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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if ((env->hflags & MIPS_HFLAG_BMASK) != 0
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&& env->active_tc.PC != tb->pc) {
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env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
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env->hflags &= ~MIPS_HFLAG_BMASK;
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return true;
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}
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return false;
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}
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# endif /* !CONFIG_USER_ONLY */
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#endif /* CONFIG_TCG */
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static bool mips_cpu_has_work(CPUState *cs)
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@ -679,6 +696,7 @@ static struct TCGCPUOps mips_tcg_ops = {
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.do_interrupt = mips_cpu_do_interrupt,
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.do_transaction_failed = mips_cpu_do_transaction_failed,
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.do_unaligned_access = mips_cpu_do_unaligned_access,
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.io_recompile_replay_branch = mips_io_recompile_replay_branch,
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#endif /* !CONFIG_USER_ONLY */
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};
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#endif /* CONFIG_TCG */
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