target/xtensa: move non-HELPER functions to helper.c
Move remaining non-HELPER functions from op_helper.c to helper.c. No functional changes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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@ -29,10 +29,8 @@
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/gdbstub.h"
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#include "exec/helper-proto.h"
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#include "qemu/host-utils.h"
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/loader.h"
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#endif
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static struct XtensaConfigList *xtensa_cores;
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@ -188,6 +186,63 @@ int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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#else
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void xtensa_cpu_do_unaligned_access(CPUState *cs,
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vaddr addr, MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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CPUXtensaState *env = &cpu->env;
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if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) &&
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!xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) {
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cpu_restore_state(CPU(cpu), retaddr, true);
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HELPER(exception_cause_vaddr)(env,
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env->pc, LOAD_STORE_ALIGNMENT_CAUSE,
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addr);
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}
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}
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void tlb_fill(CPUState *cs, target_ulong vaddr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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CPUXtensaState *env = &cpu->env;
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uint32_t paddr;
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uint32_t page_size;
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unsigned access;
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int ret = xtensa_get_physical_addr(env, true, vaddr, access_type, mmu_idx,
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&paddr, &page_size, &access);
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qemu_log_mask(CPU_LOG_MMU, "%s(%08x, %d, %d) -> %08x, ret = %d\n",
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__func__, vaddr, access_type, mmu_idx, paddr, ret);
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if (ret == 0) {
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tlb_set_page(cs,
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vaddr & TARGET_PAGE_MASK,
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paddr & TARGET_PAGE_MASK,
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access, mmu_idx, page_size);
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} else {
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cpu_restore_state(cs, retaddr, true);
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HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr);
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}
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}
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void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
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unsigned size, MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response, uintptr_t retaddr)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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CPUXtensaState *env = &cpu->env;
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cpu_restore_state(cs, retaddr, true);
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HELPER(exception_cause_vaddr)(env, env->pc,
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access_type == MMU_INST_FETCH ?
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INSTR_PIF_ADDR_ERROR_CAUSE :
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LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
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addr);
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}
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void xtensa_runstall(CPUXtensaState *env, bool runstall)
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{
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CPUState *cpu = CPU(xtensa_env_get_cpu(env));
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@ -37,62 +37,6 @@
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#ifndef CONFIG_USER_ONLY
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void xtensa_cpu_do_unaligned_access(CPUState *cs,
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vaddr addr, MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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CPUXtensaState *env = &cpu->env;
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if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) &&
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!xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) {
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cpu_restore_state(CPU(cpu), retaddr, true);
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HELPER(exception_cause_vaddr)(env,
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env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
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}
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}
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void tlb_fill(CPUState *cs, target_ulong vaddr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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CPUXtensaState *env = &cpu->env;
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uint32_t paddr;
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uint32_t page_size;
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unsigned access;
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int ret = xtensa_get_physical_addr(env, true, vaddr, access_type, mmu_idx,
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&paddr, &page_size, &access);
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qemu_log_mask(CPU_LOG_MMU, "%s(%08x, %d, %d) -> %08x, ret = %d\n",
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__func__, vaddr, access_type, mmu_idx, paddr, ret);
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if (ret == 0) {
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tlb_set_page(cs,
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vaddr & TARGET_PAGE_MASK,
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paddr & TARGET_PAGE_MASK,
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access, mmu_idx, page_size);
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} else {
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cpu_restore_state(cs, retaddr, true);
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HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr);
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}
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}
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void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
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unsigned size, MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response, uintptr_t retaddr)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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CPUXtensaState *env = &cpu->env;
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cpu_restore_state(cs, retaddr, true);
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HELPER(exception_cause_vaddr)(env, env->pc,
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access_type == MMU_INST_FETCH ?
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INSTR_PIF_ADDR_ERROR_CAUSE :
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LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
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addr);
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}
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void HELPER(update_ccount)(CPUXtensaState *env)
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{
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uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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