diff --git a/dtc b/dtc
index fa8bc7f928..558cd81bdd 160000
--- a/dtc
+++ b/dtc
@@ -1 +1 @@
-Subproject commit fa8bc7f928ac25f23532afc8beb2073efc8fb063
+Subproject commit 558cd81bdd432769b59bff01240c44f82cfb1a9d
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index c3bb991605..6ee566d658 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -3163,8 +3163,13 @@ DEFINE_SPAPR_MACHINE(2_9, "2.9", true);
 /*
  * pseries-2.8
  */
-#define SPAPR_COMPAT_2_8                            \
-    HW_COMPAT_2_8
+#define SPAPR_COMPAT_2_8                                        \
+    HW_COMPAT_2_8                                               \
+    {                                                           \
+        .driver   = TYPE_SPAPR_PCI_HOST_BRIDGE,                 \
+        .property = "pcie-extended-configuration-space",        \
+        .value    = "off",                                      \
+    },
 
 static void spapr_machine_2_8_instance_options(MachineState *machine)
 {
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 919d3c2c59..98c52e411f 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -1321,7 +1321,7 @@ static int spapr_populate_pci_child_dt(PCIDevice *dev, void *fdt, int offset,
     _FDT(fdt_setprop(fdt, offset, "assigned-addresses",
                      (uint8_t *)rp.assigned, rp.assigned_len));
 
-    if (pci_is_express(dev)) {
+    if (sphb->pcie_ecs && pci_is_express(dev)) {
         _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1));
     }
 
@@ -1858,6 +1858,8 @@ static Property spapr_phb_properties[] = {
     DEFINE_PROP_UINT32("numa_node", sPAPRPHBState, numa_node, -1),
     DEFINE_PROP_BOOL("pre-2.8-migration", sPAPRPHBState,
                      pre_2_8_migration, false),
+    DEFINE_PROP_BOOL("pcie-extended-configuration-space", sPAPRPHBState,
+                     pcie_ecs, true),
     DEFINE_PROP_END_OF_LIST(),
 };
 
diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h
index dfa76143f3..1c2e970da2 100644
--- a/include/hw/pci-host/spapr.h
+++ b/include/hw/pci-host/spapr.h
@@ -80,6 +80,8 @@ struct sPAPRPHBState {
 
     uint32_t numa_node;
 
+    bool pcie_ecs; /* Allow access to PCIe extended config space? */
+
     /* Fields for migration compatibility hacks */
     bool pre_2_8_migration;
     uint32_t mig_liobn;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 7c4a1f50b3..5ee33b3fd3 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1408,7 +1408,7 @@ int ppc_compat_max_threads(PowerPCCPU *cpu);
 #define SPR_601_UDECR         (0x006)
 #define SPR_LR                (0x008)
 #define SPR_CTR               (0x009)
-#define SPR_UAMR              (0x00C)
+#define SPR_UAMR              (0x00D)
 #define SPR_DSCR              (0x011)
 #define SPR_DSISR             (0x012)
 #define SPR_DAR               (0x013) /* DAE for PowerPC 601 */
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b6abc60a00..f40b5a1abf 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -818,7 +818,7 @@ static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
         if (is_isa300(ctx)) {
             tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
         }
-        tcg_gen_extract_tl(cpu_ov, cpu_ov, 63, 1);
+        tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
     }
     tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
 }