mirrors
/
qemu
mirror of https://gitlab.com/qemu-project/qemu
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs 

Replace type2_trigger_t with the real tdata1, tdata2, and tdata3 CSRs,
which allows us to support more types of triggers in the future.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20220909134215.1843865-4-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2022-09-09 21:42:10 +08:00 committed by Alistair Francis
parent 9d5a84db91
commit 9495c4888a
4 changed files with 48 additions and 88 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
target/riscv/cpu.h
View File

@ -324,7 +324,11 @@ struct CPUArchState {
/* trigger module */ /* trigger module */
target_ulong trigger_cur; target_ulong trigger_cur;
type2_trigger_t type2_trig[RV_MAX_TRIGGERS]; target_ulong tdata1[RV_MAX_TRIGGERS];
target_ulong tdata2[RV_MAX_TRIGGERS];
target_ulong tdata3[RV_MAX_TRIGGERS];
struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS];
struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS];
/* machine specific rdtime callback */ /* machine specific rdtime callback */
uint64_t (*rdtime_fn)(void *); uint64_t (*rdtime_fn)(void *);

103
target/riscv/debug.c
View File

@ -91,8 +91,7 @@ static inline target_ulong extract_trigger_type(CPURISCVState *env,
static inline target_ulong get_trigger_type(CPURISCVState *env, static inline target_ulong get_trigger_type(CPURISCVState *env,
target_ulong trigger_index) target_ulong trigger_index)
{ {
target_ulong tdata1 = env->type2_trig[trigger_index].mcontrol; return extract_trigger_type(env, env->tdata1[trigger_index]);
return extract_trigger_type(env, tdata1);
} }
static inline target_ulong build_tdata1(CPURISCVState *env, static inline target_ulong build_tdata1(CPURISCVState *env,
@ -188,6 +187,8 @@ static inline void warn_always_zero_bit(target_ulong val, target_ulong mask,
} }
} }
/* type 2 trigger */
static uint32_t type2_breakpoint_size(CPURISCVState *env, target_ulong ctrl) static uint32_t type2_breakpoint_size(CPURISCVState *env, target_ulong ctrl)
{ {
uint32_t size, sizelo, sizehi = 0; uint32_t size, sizelo, sizehi = 0;
@ -247,8 +248,8 @@ static target_ulong type2_mcontrol_validate(CPURISCVState *env,
static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index) static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index)
{ {
target_ulong ctrl = env->type2_trig[index].mcontrol; target_ulong ctrl = env->tdata1[index];
target_ulong addr = env->type2_trig[index].maddress; target_ulong addr = env->tdata2[index];
bool enabled = type2_breakpoint_enabled(ctrl); bool enabled = type2_breakpoint_enabled(ctrl);
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
@ -259,7 +260,7 @@ static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index)
} }
if (ctrl & TYPE2_EXEC) { if (ctrl & TYPE2_EXEC) {
cpu_breakpoint_insert(cs, addr, flags, &env->type2_trig[index].bp); cpu_breakpoint_insert(cs, addr, flags, &env->cpu_breakpoint[index]);
} }
if (ctrl & TYPE2_LOAD) { if (ctrl & TYPE2_LOAD) {
@ -273,10 +274,10 @@ static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index)
size = type2_breakpoint_size(env, ctrl); size = type2_breakpoint_size(env, ctrl);
if (size != 0) { if (size != 0) {
cpu_watchpoint_insert(cs, addr, size, flags, cpu_watchpoint_insert(cs, addr, size, flags,
&env->type2_trig[index].wp); &env->cpu_watchpoint[index]);
} else { } else {
cpu_watchpoint_insert(cs, addr, 8, flags, cpu_watchpoint_insert(cs, addr, 8, flags,
&env->type2_trig[index].wp); &env->cpu_watchpoint[index]);
} }
} }
} }
@ -285,36 +286,17 @@ static void type2_breakpoint_remove(CPURISCVState *env, target_ulong index)
{ {
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
if (env->type2_trig[index].bp) { if (env->cpu_breakpoint[index]) {
cpu_breakpoint_remove_by_ref(cs, env->type2_trig[index].bp); cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[index]);
env->type2_trig[index].bp = NULL; env->cpu_breakpoint[index] = NULL;
} }
if (env->type2_trig[index].wp) { if (env->cpu_watchpoint[index]) {
cpu_watchpoint_remove_by_ref(cs, env->type2_trig[index].wp); cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]);
env->type2_trig[index].wp = NULL; env->cpu_watchpoint[index] = NULL;
} }
} }
static target_ulong type2_reg_read(CPURISCVState *env,
target_ulong index, int tdata_index)
{
target_ulong tdata;
switch (tdata_index) {
case TDATA1:
tdata = env->type2_trig[index].mcontrol;
break;
case TDATA2:
tdata = env->type2_trig[index].maddress;
break;
default:
g_assert_not_reached();
}
return tdata;
}
static void type2_reg_write(CPURISCVState *env, target_ulong index, static void type2_reg_write(CPURISCVState *env, target_ulong index,
int tdata_index, target_ulong val) int tdata_index, target_ulong val)
{ {
@ -323,19 +305,23 @@ static void type2_reg_write(CPURISCVState *env, target_ulong index,
switch (tdata_index) { switch (tdata_index) {
case TDATA1: case TDATA1:
new_val = type2_mcontrol_validate(env, val); new_val = type2_mcontrol_validate(env, val);
if (new_val != env->type2_trig[index].mcontrol) { if (new_val != env->tdata1[index]) {
env->type2_trig[index].mcontrol = new_val; env->tdata1[index] = new_val;
type2_breakpoint_remove(env, index); type2_breakpoint_remove(env, index);
type2_breakpoint_insert(env, index); type2_breakpoint_insert(env, index);
} }
break; break;
case TDATA2: case TDATA2:
if (val != env->type2_trig[index].maddress) { if (val != env->tdata2[index]) {
env->type2_trig[index].maddress = val; env->tdata2[index] = val;
type2_breakpoint_remove(env, index); type2_breakpoint_remove(env, index);
type2_breakpoint_insert(env, index); type2_breakpoint_insert(env, index);
} }
break; break;
case TDATA3:
qemu_log_mask(LOG_UNIMP,
"tdata3 is not supported for type 2 trigger\n");
break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
} }
@ -345,30 +331,16 @@ static void type2_reg_write(CPURISCVState *env, target_ulong index,
target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index) target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
{ {
int trigger_type = get_trigger_type(env, env->trigger_cur); switch (tdata_index) {
case TDATA1:
switch (trigger_type) { return env->tdata1[env->trigger_cur];
case TRIGGER_TYPE_AD_MATCH: case TDATA2:
return type2_reg_read(env, env->trigger_cur, tdata_index); return env->tdata2[env->trigger_cur];
break; case TDATA3:
case TRIGGER_TYPE_INST_CNT: return env->tdata3[env->trigger_cur];
case TRIGGER_TYPE_INT:
case TRIGGER_TYPE_EXCP:
case TRIGGER_TYPE_AD_MATCH6:
case TRIGGER_TYPE_EXT_SRC:
qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n",
trigger_type);
break;
case TRIGGER_TYPE_NO_EXIST:
case TRIGGER_TYPE_UNAVAIL:
qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n",
trigger_type);
break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
} }
return 0;
} }
void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val) void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
@ -436,8 +408,8 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
switch (trigger_type) { switch (trigger_type) {
case TRIGGER_TYPE_AD_MATCH: case TRIGGER_TYPE_AD_MATCH:
ctrl = env->type2_trig[i].mcontrol; ctrl = env->tdata1[i];
pc = env->type2_trig[i].maddress; pc = env->tdata2[i];
if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) { if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
/* check U/S/M bit against current privilege level */ /* check U/S/M bit against current privilege level */
@ -471,8 +443,8 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
switch (trigger_type) { switch (trigger_type) {
case TRIGGER_TYPE_AD_MATCH: case TRIGGER_TYPE_AD_MATCH:
ctrl = env->type2_trig[i].mcontrol; ctrl = env->tdata1[i];
addr = env->type2_trig[i].maddress; addr = env->tdata2[i];
flags = 0; flags = 0;
if (ctrl & TYPE2_LOAD) { if (ctrl & TYPE2_LOAD) {
@ -518,9 +490,10 @@ void riscv_trigger_init(CPURISCVState *env)
* chain = 0 (unimplemented, always 0) * chain = 0 (unimplemented, always 0)
* match = 0 (always 0, when any compare value equals tdata2) * match = 0 (always 0, when any compare value equals tdata2)
*/ */
env->type2_trig[i].mcontrol = tdata1; env->tdata1[i] = tdata1;
env->type2_trig[i].maddress = 0; env->tdata2[i] = 0;
env->type2_trig[i].bp = NULL; env->tdata3[i] = 0;
env->type2_trig[i].wp = NULL; env->cpu_breakpoint[i] = NULL;
env->cpu_watchpoint[i] = NULL;
} }
} }

7
target/riscv/debug.h
View File

@ -44,13 +44,6 @@ typedef enum {
TRIGGER_TYPE_NUM TRIGGER_TYPE_NUM
} trigger_type_t; } trigger_type_t;
typedef struct {
target_ulong mcontrol;
target_ulong maddress;
struct CPUBreakpoint *bp;
struct CPUWatchpoint *wp;
} type2_trigger_t;
/* tdata1 field masks */ /* tdata1 field masks */
#define RV32_TYPE(t) ((uint32_t)(t) << 28) #define RV32_TYPE(t) ((uint32_t)(t) << 28)

20
target/riscv/machine.c
View File

@ -229,26 +229,16 @@ static bool debug_needed(void *opaque)
return riscv_feature(env, RISCV_FEATURE_DEBUG); return riscv_feature(env, RISCV_FEATURE_DEBUG);
} }
static const VMStateDescription vmstate_debug_type2 = {
.name = "cpu/debug/type2",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINTTL(mcontrol, type2_trigger_t),
VMSTATE_UINTTL(maddress, type2_trigger_t),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_debug = { static const VMStateDescription vmstate_debug = {
.name = "cpu/debug", .name = "cpu/debug",
.version_id = 1, .version_id = 2,
.minimum_version_id = 1, .minimum_version_id = 2,
.needed = debug_needed, .needed = debug_needed,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_UINTTL(env.trigger_cur, RISCVCPU), VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, RV_MAX_TRIGGERS, VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),
0, vmstate_debug_type2, type2_trigger_t), VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS),
VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };