vt82c686: Reorganise code
Move lines around so that object definitions become consecutive and not scattered around. This brings functions belonging to an object together so it's clearer what is defined and what parts belong to which object. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <9f942989dba46fc1c23b881f6cb135948f818c2f.1610223397.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
BALATON Zoltan
Philippe Mathieu-Daudé
parent
6be6e4bc76
commit
94349bffda
@ -26,112 +26,7 @@
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#include "exec/address-spaces.h"
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#include "trace.h"
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typedef struct SuperIOConfig {
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uint8_t regs[0x100];
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uint8_t index;
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MemoryRegion io;
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} SuperIOConfig;
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struct VT82C686BISAState {
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PCIDevice dev;
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SuperIOConfig superio_cfg;
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};
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OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA)
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static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned size)
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{
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SuperIOConfig *sc = opaque;
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if (addr == 0x3f0) { /* config index register */
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sc->index = data & 0xff;
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} else {
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bool can_write = true;
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/* 0x3f1, config data register */
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trace_via_superio_write(sc->index, data & 0xff);
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switch (sc->index) {
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case 0x00 ... 0xdf:
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case 0xe4:
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case 0xe5:
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case 0xe9 ... 0xed:
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case 0xf3:
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case 0xf5:
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case 0xf7:
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case 0xf9 ... 0xfb:
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case 0xfd ... 0xff:
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can_write = false;
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break;
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/* case 0xe6 ... 0xe8: Should set base port of parallel and serial */
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default:
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break;
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}
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if (can_write) {
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sc->regs[sc->index] = data & 0xff;
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}
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}
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}
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static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size)
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{
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SuperIOConfig *sc = opaque;
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uint8_t val = sc->regs[sc->index];
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trace_via_superio_read(sc->index, val);
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return val;
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}
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static const MemoryRegionOps superio_cfg_ops = {
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.read = superio_cfg_read,
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.write = superio_cfg_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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};
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static void vt82c686b_isa_reset(DeviceState *dev)
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{
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VT82C686BISAState *s = VT82C686B_ISA(dev);
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uint8_t *pci_conf = s->dev.config;
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pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
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pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
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pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
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pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
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pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
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pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
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pci_conf[0x59] = 0x04;
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pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
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pci_conf[0x5f] = 0x04;
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pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
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s->superio_cfg.regs[0xe0] = 0x3c; /* Device ID */
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s->superio_cfg.regs[0xe2] = 0x03; /* Function select */
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s->superio_cfg.regs[0xe3] = 0xfc; /* Floppy ctrl base addr */
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s->superio_cfg.regs[0xe6] = 0xde; /* Parallel port base addr */
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s->superio_cfg.regs[0xe7] = 0xfe; /* Serial port 1 base addr */
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s->superio_cfg.regs[0xe8] = 0xbe; /* Serial port 2 base addr */
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}
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/* write config pci function0 registers. PCI-ISA bridge */
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static void vt82c686b_write_config(PCIDevice *d, uint32_t addr,
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uint32_t val, int len)
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{
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VT82C686BISAState *s = VT82C686B_ISA(d);
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trace_via_isa_write(addr, val, len);
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pci_default_write_config(d, addr, val, len);
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if (addr == 0x85) {
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/* BIT(1): enable or disable superio config io ports */
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memory_region_set_enabled(&s->superio_cfg.io, val & BIT(1));
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}
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}
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OBJECT_DECLARE_SIMPLE_TYPE(VT686PMState, VT82C686B_PM)
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struct VT686PMState {
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PCIDevice dev;
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@ -142,30 +37,6 @@ struct VT686PMState {
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uint32_t smb_io_base;
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};
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OBJECT_DECLARE_SIMPLE_TYPE(VT686PMState, VT82C686B_PM)
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static void pm_update_sci(VT686PMState *s)
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{
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int sci_level, pmsts;
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pmsts = acpi_pm1_evt_get_sts(&s->ar);
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sci_level = (((pmsts & s->ar.pm1.evt.en) &
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(ACPI_BITMASK_RT_CLOCK_ENABLE |
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ACPI_BITMASK_POWER_BUTTON_ENABLE |
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ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
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ACPI_BITMASK_TIMER_ENABLE)) != 0);
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pci_set_irq(&s->dev, sci_level);
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/* schedule a timer interruption if needed */
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acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
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!(pmsts & ACPI_BITMASK_TIMER_STATUS));
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}
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static void pm_tmr_timer(ACPIREGS *ar)
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{
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VT686PMState *s = container_of(ar, VT686PMState, ar);
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pm_update_sci(s);
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}
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static void pm_io_space_update(VT686PMState *s)
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{
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uint32_t pm_io_base;
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@ -179,12 +50,6 @@ static void pm_io_space_update(VT686PMState *s)
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memory_region_transaction_commit();
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}
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static void pm_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len)
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{
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trace_via_pm_write(addr, val, len);
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pci_default_write_config(d, addr, val, len);
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}
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static int vmstate_acpi_post_load(void *opaque, int version_id)
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{
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VT686PMState *s = opaque;
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@ -210,7 +75,34 @@ static const VMStateDescription vmstate_acpi = {
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}
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};
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/* vt82c686 pm init */
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static void pm_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len)
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{
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trace_via_pm_write(addr, val, len);
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pci_default_write_config(d, addr, val, len);
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}
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static void pm_update_sci(VT686PMState *s)
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{
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int sci_level, pmsts;
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pmsts = acpi_pm1_evt_get_sts(&s->ar);
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sci_level = (((pmsts & s->ar.pm1.evt.en) &
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(ACPI_BITMASK_RT_CLOCK_ENABLE |
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ACPI_BITMASK_POWER_BUTTON_ENABLE |
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ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
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ACPI_BITMASK_TIMER_ENABLE)) != 0);
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pci_set_irq(&s->dev, sci_level);
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/* schedule a timer interruption if needed */
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acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
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!(pmsts & ACPI_BITMASK_TIMER_STATUS));
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}
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static void pm_tmr_timer(ACPIREGS *ar)
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{
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VT686PMState *s = container_of(ar, VT686PMState, ar);
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pm_update_sci(s);
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}
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static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp)
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{
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VT686PMState *s = VT82C686B_PM(dev);
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@ -276,6 +168,87 @@ static const TypeInfo via_pm_info = {
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},
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};
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typedef struct SuperIOConfig {
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uint8_t regs[0x100];
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uint8_t index;
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MemoryRegion io;
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} SuperIOConfig;
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static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned size)
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{
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SuperIOConfig *sc = opaque;
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if (addr == 0x3f0) { /* config index register */
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sc->index = data & 0xff;
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} else {
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bool can_write = true;
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/* 0x3f1, config data register */
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trace_via_superio_write(sc->index, data & 0xff);
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switch (sc->index) {
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case 0x00 ... 0xdf:
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case 0xe4:
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case 0xe5:
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case 0xe9 ... 0xed:
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case 0xf3:
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case 0xf5:
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case 0xf7:
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case 0xf9 ... 0xfb:
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case 0xfd ... 0xff:
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can_write = false;
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break;
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/* case 0xe6 ... 0xe8: Should set base port of parallel and serial */
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default:
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break;
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}
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if (can_write) {
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sc->regs[sc->index] = data & 0xff;
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}
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}
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}
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static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size)
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{
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SuperIOConfig *sc = opaque;
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uint8_t val = sc->regs[sc->index];
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trace_via_superio_read(sc->index, val);
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return val;
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}
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static const MemoryRegionOps superio_cfg_ops = {
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.read = superio_cfg_read,
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.write = superio_cfg_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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};
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OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA)
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struct VT82C686BISAState {
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PCIDevice dev;
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SuperIOConfig superio_cfg;
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};
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static void vt82c686b_write_config(PCIDevice *d, uint32_t addr,
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uint32_t val, int len)
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{
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VT82C686BISAState *s = VT82C686B_ISA(d);
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trace_via_isa_write(addr, val, len);
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pci_default_write_config(d, addr, val, len);
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if (addr == 0x85) {
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/* BIT(1): enable or disable superio config io ports */
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memory_region_set_enabled(&s->superio_cfg.io, val & BIT(1));
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}
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}
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static const VMStateDescription vmstate_via = {
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.name = "vt82c686b",
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.version_id = 1,
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@ -286,7 +259,33 @@ static const VMStateDescription vmstate_via = {
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}
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};
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/* init the PCI-to-ISA bridge */
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static void vt82c686b_isa_reset(DeviceState *dev)
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{
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VT82C686BISAState *s = VT82C686B_ISA(dev);
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uint8_t *pci_conf = s->dev.config;
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pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
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pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
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pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
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pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
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pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
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pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
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pci_conf[0x59] = 0x04;
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pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
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pci_conf[0x5f] = 0x04;
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pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
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s->superio_cfg.regs[0xe0] = 0x3c; /* Device ID */
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s->superio_cfg.regs[0xe2] = 0x03; /* Function select */
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s->superio_cfg.regs[0xe3] = 0xfc; /* Floppy ctrl base addr */
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s->superio_cfg.regs[0xe6] = 0xde; /* Parallel port base addr */
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s->superio_cfg.regs[0xe7] = 0xfe; /* Serial port 1 base addr */
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s->superio_cfg.regs[0xe8] = 0xbe; /* Serial port 2 base addr */
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}
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static void vt82c686b_realize(PCIDevice *d, Error **errp)
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{
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VT82C686BISAState *s = VT82C686B_ISA(d);
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@ -354,6 +353,7 @@ static const TypeInfo via_info = {
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},
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};
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static void vt82c686b_superio_class_init(ObjectClass *klass, void *data)
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{
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ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
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@ -372,11 +372,12 @@ static const TypeInfo via_superio_info = {
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.class_init = vt82c686b_superio_class_init,
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};
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static void vt82c686b_register_types(void)
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{
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type_register_static(&via_pm_info);
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type_register_static(&via_superio_info);
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type_register_static(&via_info);
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type_register_static(&via_superio_info);
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}
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type_init(vt82c686b_register_types)
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