mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

hw/gpio/aspeed: Support to set the different memory size

Browse Source 
According to the datasheet of ASPEED SOCs, a GPIO controller owns 4KB of
register space for AST2700, AST2500, AST2400 and AST1030; owns 2KB of
register space for AST2600 1.8v and owns 2KB of register space for
AST2600 3.3v.

It set the memory region size 2KB by default and it does not compatible
register space for AST2700.

Introduce a new class attribute to set the GPIO controller memory size
for different ASPEED SOCs.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2024-10-01 10:43:28 +08:00 committed by Cédric Le Goater
parent 33343bff71
commit 9422dbd10b
2 changed files with 7 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
hw/gpio/aspeed_gpio.c
View File

@ -1047,7 +1047,7 @@ static void aspeed_gpio_realize(DeviceState *dev, Error **errp)
} }
memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s, memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s,
TYPE_ASPEED_GPIO, 0x800); TYPE_ASPEED_GPIO, agc->mem_size);
sysbus_init_mmio(sbd, &s->iomem); sysbus_init_mmio(sbd, &s->iomem);
} }
@ -1130,6 +1130,7 @@ static void aspeed_gpio_ast2400_class_init(ObjectClass *klass, void *data)
agc->nr_gpio_sets = 7; agc->nr_gpio_sets = 7;
agc->reg_table = aspeed_3_3v_gpios; agc->reg_table = aspeed_3_3v_gpios;
agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE; agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE;
agc->mem_size = 0x1000;
} }
static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data) static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data)
@ -1141,6 +1142,7 @@ static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data)
agc->nr_gpio_sets = 8; agc->nr_gpio_sets = 8;
agc->reg_table = aspeed_3_3v_gpios; agc->reg_table = aspeed_3_3v_gpios;
agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE; agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE;
agc->mem_size = 0x1000;
} }
static void aspeed_gpio_ast2600_3_3v_class_init(ObjectClass *klass, void *data) static void aspeed_gpio_ast2600_3_3v_class_init(ObjectClass *klass, void *data)
@ -1152,6 +1154,7 @@ static void aspeed_gpio_ast2600_3_3v_class_init(ObjectClass *klass, void *data)
agc->nr_gpio_sets = 7; agc->nr_gpio_sets = 7;
agc->reg_table = aspeed_3_3v_gpios; agc->reg_table = aspeed_3_3v_gpios;
agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE; agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE;
agc->mem_size = 0x800;
} }
static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *data) static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *data)
@ -1163,6 +1166,7 @@ static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *data)
agc->nr_gpio_sets = 2; agc->nr_gpio_sets = 2;
agc->reg_table = aspeed_1_8v_gpios; agc->reg_table = aspeed_1_8v_gpios;
agc->reg_table_count = GPIO_1_8V_REG_ARRAY_SIZE; agc->reg_table_count = GPIO_1_8V_REG_ARRAY_SIZE;
agc->mem_size = 0x800;
} }
static void aspeed_gpio_1030_class_init(ObjectClass *klass, void *data) static void aspeed_gpio_1030_class_init(ObjectClass *klass, void *data)
@ -1174,6 +1178,7 @@ static void aspeed_gpio_1030_class_init(ObjectClass *klass, void *data)
agc->nr_gpio_sets = 6; agc->nr_gpio_sets = 6;
agc->reg_table = aspeed_3_3v_gpios; agc->reg_table = aspeed_3_3v_gpios;
agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE; agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE;
agc->mem_size = 0x1000;
} }
static const TypeInfo aspeed_gpio_info = { static const TypeInfo aspeed_gpio_info = {

1
include/hw/gpio/aspeed_gpio.h
View File

@ -76,6 +76,7 @@ struct AspeedGPIOClass {
uint32_t nr_gpio_sets; uint32_t nr_gpio_sets;
const AspeedGPIOReg *reg_table; const AspeedGPIOReg *reg_table;
unsigned reg_table_count; unsigned reg_table_count;
uint64_t mem_size;
}; };
struct AspeedGPIOState { struct AspeedGPIOState {