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target-mips: make sure constants are in the second argument

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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2009-09-28 23:40:59 +02:00
parent cc739bb0c4
commit 941694d09a
1 changed files with 7 additions and 7 deletions
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14
target-mips/translate.c
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@ -803,9 +803,9 @@ generate_exception (DisasContext *ctx, int excp)
} }
/* Addresses computation */ /* Addresses computation */
static inline void gen_op_addr_add (DisasContext *ctx, TCGv t0, TCGv t1) static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)
{ {
tcg_gen_add_tl(t0, t0, t1); tcg_gen_add_tl(ret, arg0, arg1);
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
/* For compatibility with 32-bit code, data reference in user mode /* For compatibility with 32-bit code, data reference in user mode
@ -813,7 +813,7 @@ static inline void gen_op_addr_add (DisasContext *ctx, TCGv t0, TCGv t1)
See the MIPS64 PRA manual, section 4.10. */ See the MIPS64 PRA manual, section 4.10. */
if (((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && if (((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
!(ctx->hflags & MIPS_HFLAG_UX)) { !(ctx->hflags & MIPS_HFLAG_UX)) {
tcg_gen_ext32s_i64(t0, t0); tcg_gen_ext32s_i64(ret, ret);
} }
#endif #endif
} }
@ -1005,7 +1005,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
gen_load_gpr(t0, base); gen_load_gpr(t0, base);
} else { } else {
tcg_gen_movi_tl(t0, offset); tcg_gen_movi_tl(t0, offset);
gen_op_addr_add(ctx, t0, cpu_gpr[base]); gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
} }
/* Don't do NOP if destination is zero: we must perform the actual /* Don't do NOP if destination is zero: we must perform the actual
memory access. */ memory access. */
@ -1163,7 +1163,7 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
gen_load_gpr(t0, base); gen_load_gpr(t0, base);
} else { } else {
tcg_gen_movi_tl(t0, offset); tcg_gen_movi_tl(t0, offset);
gen_op_addr_add(ctx, t0, cpu_gpr[base]); gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
} }
/* Don't do NOP if destination is zero: we must perform the actual /* Don't do NOP if destination is zero: we must perform the actual
memory access. */ memory access. */
@ -1202,7 +1202,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
gen_load_gpr(t0, base); gen_load_gpr(t0, base);
} else { } else {
tcg_gen_movi_tl(t0, offset); tcg_gen_movi_tl(t0, offset);
gen_op_addr_add(ctx, t0, cpu_gpr[base]); gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
} }
/* Don't do NOP if destination is zero: we must perform the actual /* Don't do NOP if destination is zero: we must perform the actual
memory access. */ memory access. */
@ -7264,7 +7264,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
gen_load_gpr(t0, base); gen_load_gpr(t0, base);
} else { } else {
gen_load_gpr(t0, index); gen_load_gpr(t0, index);
gen_op_addr_add(ctx, t0, cpu_gpr[base]); gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
} }
/* Don't do NOP if destination is zero: we must perform the actual /* Don't do NOP if destination is zero: we must perform the actual
memory access. */ memory access. */