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target-arm queue:

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* Don't report Statistical Profiling Extension in ID registers
  * virt ACPI tables: Present the GICR structure properly for GICv4
  * Fix some typos in documentation
  * tests/unit: fix a -Wformat-truncation warning
  * cutils: Add missing dyld(3) include on macOS
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Merge tag 'pull-target-arm-20220812' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Don't report Statistical Profiling Extension in ID registers
 * virt ACPI tables: Present the GICR structure properly for GICv4
 * Fix some typos in documentation
 * tests/unit: fix a -Wformat-truncation warning
 * cutils: Add missing dyld(3) include on macOS

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# gpg: Signature made Fri 12 Aug 2022 04:43:58 AM PDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]

* tag 'pull-target-arm-20220812' of https://git.linaro.org/people/pmaydell/qemu-arm:
  cutils: Add missing dyld(3) include on macOS
  hw/arm/virt-acpi-build: Present the GICR structure properly for GICv4
  tests/unit: fix a -Wformat-truncation warning
  Fix some typos in documentation (most of them found by codespell)
  target/arm: Don't report Statistical Profiling Extension in ID registers

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-08-12 10:46:43 -07:00
commit 93f3dd6048
9 changed files with 31 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
docs/about/deprecated.rst
View File

@ -297,7 +297,7 @@ by using ``-machine graphics=off``.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
In QEMU versions 6.1, 6.2 and 7.0, the ``nvme-ns`` generates an EUI-64 In QEMU versions 6.1, 6.2 and 7.0, the ``nvme-ns`` generates an EUI-64
identifer that is not globally unique. If an EUI-64 identifer is required, the identifier that is not globally unique. If an EUI-64 identifier is required, the
user must set it explicitly using the ``nvme-ns`` device parameter ``eui64``. user must set it explicitly using the ``nvme-ns`` device parameter ``eui64``.
``-device nvme,use-intel-id=on|off`` (since 7.1) ``-device nvme,use-intel-id=on|off`` (since 7.1)

4
docs/specs/acpi_erst.rst
View File

@ -108,7 +108,7 @@ Slot 0 contains a backend storage header that identifies the contents
as ERST and also facilitates efficient access to the records. as ERST and also facilitates efficient access to the records.
Depending upon the size of the backend storage, additional slots will Depending upon the size of the backend storage, additional slots will
be designated to be a part of the slot 0 header. For example, at 8KiB, be designated to be a part of the slot 0 header. For example, at 8KiB,
the slot 0 header can accomodate 1021 records. Thus a storage size the slot 0 header can accommodate 1021 records. Thus a storage size
of 8MiB (8KiB * 1024) requires an additional slot for use by the of 8MiB (8KiB * 1024) requires an additional slot for use by the
header. In this scenario, slot 0 and slot 1 form the backend storage header. In this scenario, slot 0 and slot 1 form the backend storage
header, and records can be stored starting at slot 2. header, and records can be stored starting at slot 2.
@ -196,5 +196,5 @@ References
[2] "Unified Extensible Firmware Interface Specification", [2] "Unified Extensible Firmware Interface Specification",
version 2.1, October 2008. version 2.1, October 2008.
[3] "Windows Hardware Error Architecture", specfically [3] "Windows Hardware Error Architecture", specifically
"Error Record Persistence Mechanism". "Error Record Persistence Mechanism".

8
docs/system/devices/canokey.rst
View File

@ -28,9 +28,9 @@ With the same software configuration as a hardware key,
the guest OS can use all the functionalities of a secure key as if the guest OS can use all the functionalities of a secure key as if
there was actually an hardware key plugged in. there was actually an hardware key plugged in.
CanoKey QEMU provides much convenience for debuging: CanoKey QEMU provides much convenience for debugging:
* libcanokey-qemu supports debuging output thus developers can * libcanokey-qemu supports debugging output thus developers can
inspect what happens inside a secure key inspect what happens inside a secure key
* CanoKey QEMU supports trace event thus event * CanoKey QEMU supports trace event thus event
* QEMU USB stack supports pcap thus USB packet between the guest * QEMU USB stack supports pcap thus USB packet between the guest
@ -102,8 +102,8 @@ and find CanoKey QEMU there:
You may setup the key as guided in [6]_. The console for the key is at [7]_. You may setup the key as guided in [6]_. The console for the key is at [7]_.
Debuging Debugging
======== =========
CanoKey QEMU consists of two parts, ``libcanokey-qemu.so`` and ``canokey.c``, CanoKey QEMU consists of two parts, ``libcanokey-qemu.so`` and ``canokey.c``,
the latter of which resides in QEMU. The former provides core functionality the latter of which resides in QEMU. The former provides core functionality

12
docs/system/devices/cxl.rst
View File

@ -83,7 +83,7 @@ CXL Fixed Memory Windows (CFMW)
A CFMW consists of a particular range of Host Physical Address space A CFMW consists of a particular range of Host Physical Address space
which is routed to particular CXL Host Bridges. At time of generic which is routed to particular CXL Host Bridges. At time of generic
software initialization it will have a particularly interleaving software initialization it will have a particularly interleaving
configuration and associated Quality of Serice Throtling Group (QTG). configuration and associated Quality of Service Throttling Group (QTG).
This information is available to system software, when making This information is available to system software, when making
decisions about how to configure interleave across available CXL decisions about how to configure interleave across available CXL
memory devices. It is provide as CFMW Structures (CFMWS) in memory devices. It is provide as CFMW Structures (CFMWS) in
@ -98,7 +98,7 @@ specification defined register interface called CXL Host Bridge
Component Registers (CHBCR). The location of this CHBCR MMIO Component Registers (CHBCR). The location of this CHBCR MMIO
space is described to system software via a CXL Host Bridge space is described to system software via a CXL Host Bridge
Structure (CHBS) in the CEDT ACPI table. The actual interfaces Structure (CHBS) in the CEDT ACPI table. The actual interfaces
are identical to those used for other parts of the CXL heirarchy are identical to those used for other parts of the CXL hierarchy
as CXL Component Registers in PCI BARs. as CXL Component Registers in PCI BARs.
Interfaces provided include: Interfaces provided include:
@ -143,7 +143,7 @@ CXL Memory Devices - Type 3
~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~
CXL type 3 devices use a PCI class code and are intended to be supported CXL type 3 devices use a PCI class code and are intended to be supported
by a generic operating system driver. They have HDM decoders by a generic operating system driver. They have HDM decoders
though in these EP devices, the decoder is reponsible not for though in these EP devices, the decoder is responsible not for
routing but for translation of the incoming host physical address (HPA) routing but for translation of the incoming host physical address (HPA)
into a Device Physical Address (DPA). into a Device Physical Address (DPA).
@ -209,7 +209,7 @@ Notes:
ranges of the system physical address map. Each CFMW has ranges of the system physical address map. Each CFMW has
particular interleave setup across the CXL Host Bridges (HB) particular interleave setup across the CXL Host Bridges (HB)
CFMW0 provides uninterleaved access to HB0, CFW2 provides CFMW0 provides uninterleaved access to HB0, CFW2 provides
uninterleaved acess to HB1. CFW1 provides interleaved memory access uninterleaved access to HB1. CFW1 provides interleaved memory access
across HB0 and HB1. across HB0 and HB1.
(2) **Two CXL Host Bridges**. Each of these has 2 CXL Root Ports and (2) **Two CXL Host Bridges**. Each of these has 2 CXL Root Ports and
@ -282,7 +282,7 @@ Example topology involving a switch::
--------------------------------------------------- ---------------------------------------------------
| Switch 0 USP as PCI 0d:00.0 | | Switch 0 USP as PCI 0d:00.0 |
| USP has HDM decoder which direct traffic to | | USP has HDM decoder which direct traffic to |
| appropiate downstream port | | appropriate downstream port |
| Switch BUS appears as 0e | | Switch BUS appears as 0e |
|x__________________________________________________| |x__________________________________________________|
| | | | | | | |
@ -366,7 +366,7 @@ An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave::
Kernel Configuration Options Kernel Configuration Options
---------------------------- ----------------------------
In Linux 5.18 the followings options are necessary to make use of In Linux 5.18 the following options are necessary to make use of
OS management of CXL memory devices as described here. OS management of CXL memory devices as described here.
* CONFIG_CXL_BUS * CONFIG_CXL_BUS

4
hw/arm/virt-acpi-build.c
View File

@ -732,7 +732,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ? uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
PPI(VIRTUAL_PMU_IRQ) : 0; PPI(VIRTUAL_PMU_IRQ) : 0;
if (vms->gic_version == 2) { if (vms->gic_version == VIRT_GIC_VERSION_2) {
physical_base_address = memmap[VIRT_GIC_CPU].base; physical_base_address = memmap[VIRT_GIC_CPU].base;
gicv = memmap[VIRT_GIC_VCPU].base; gicv = memmap[VIRT_GIC_VCPU].base;
gich = memmap[VIRT_GIC_HYP].base; gich = memmap[VIRT_GIC_HYP].base;
@ -762,7 +762,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
build_append_int_noprefix(table_data, armcpu->mp_affinity, 8); build_append_int_noprefix(table_data, armcpu->mp_affinity, 8);
} }
if (vms->gic_version == 3) { if (vms->gic_version != VIRT_GIC_VERSION_2) {
build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base, build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base,
memmap[VIRT_GIC_REDIST].size); memmap[VIRT_GIC_REDIST].size);
if (virt_gicv3_redist_region_count(vms) == 2) { if (virt_gicv3_redist_region_count(vms) == 2) {

11
target/arm/cpu.c
View File

@ -1933,6 +1933,17 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
} }
#endif #endif
if (tcg_enabled()) {
/*
* Don't report the Statistical Profiling Extension in the ID
* registers, because TCG doesn't implement it yet (not even a
* minimal stub version) and guests will fall over when they
* try to access the non-existent system registers for it.
*/
cpu->isar.id_aa64dfr0 =
FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
}
/* MPU can be configured out of a PMSA CPU either by setting has-mpu /* MPU can be configured out of a PMSA CPU either by setting has-mpu
* to false or by setting pmsav7-dregion to 0. * to false or by setting pmsav7-dregion to 0.
*/ */

3
tests/unit/test-qobject-input-visitor.c
View File

@ -447,9 +447,8 @@ static void test_visitor_in_list(TestInputVisitorData *data,
g_assert(head != NULL); g_assert(head != NULL);
for (i = 0, item = head; item; item = item->next, i++) { for (i = 0, item = head; item; item = item->next, i++) {
char string[12]; g_autofree char *string = g_strdup_printf("string%d", i);
snprintf(string, sizeof(string), "string%d", i);
g_assert_cmpstr(item->value->string, ==, string); g_assert_cmpstr(item->value->string, ==, string);
g_assert_cmpint(item->value->integer, ==, 42 + i); g_assert_cmpint(item->value->integer, ==, 42 + i);
} }

4
util/cutils.c
View File

@ -39,6 +39,10 @@
#include <kernel/image.h> #include <kernel/image.h>
#endif #endif
#ifdef __APPLE__
#include <mach-o/dyld.h>
#endif
#ifdef G_OS_WIN32 #ifdef G_OS_WIN32
#include <pathcch.h> #include <pathcch.h>
#include <wchar.h> #include <wchar.h>

4
util/oslib-posix.c
View File

@ -58,10 +58,6 @@
#include <lwp.h> #include <lwp.h>
#endif #endif
#ifdef __APPLE__
#include <mach-o/dyld.h>
#endif
#include "qemu/mmap-alloc.h" #include "qemu/mmap-alloc.h"
#ifdef CONFIG_DEBUG_STACK_USAGE #ifdef CONFIG_DEBUG_STACK_USAGE