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pull-loongarch-20231013

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Merge tag 'pull-loongarch-20231013' of https://gitlab.com/gaosong/qemu into staging

pull-loongarch-20231013

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# gpg: Signature made Thu 12 Oct 2023 22:06:45 EDT
# gpg:                using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
# gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C  6C2C 40A2 FFF2 3926 3EDF

* tag 'pull-loongarch-20231013' of https://gitlab.com/gaosong/qemu:
  LoongArch: step down as general arch maintainer
  hw/loongarch/virt: Remove unused 'loongarch_virt_pm' region
  hw/loongarch/virt: Remove unused ISA Bus
  hw/loongarch/virt: Remove unused ISA UART
  hw/loongarch: remove global loaderparams variable
  target/loongarch: Add preldx instruction
  target/loongarch: fix ASXE flag conflict

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2023-10-16 12:37:35 -04:00
commit 9390f0fd3e
9 changed files with 49 additions and 87 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
MAINTAINERS
View File

@ -248,7 +248,6 @@ F: disas/hppa.c
LoongArch TCG CPUs LoongArch TCG CPUs
M: Song Gao <gaosong@loongson.cn> M: Song Gao <gaosong@loongson.cn>
M: Xiaojuan Yang <yangxiaojuan@loongson.cn>
S: Maintained S: Maintained
F: target/loongarch/ F: target/loongarch/
F: tests/tcg/loongarch64/ F: tests/tcg/loongarch64/
@ -1191,7 +1190,6 @@ F: pc-bios/hppa-firmware.img
LoongArch Machines LoongArch Machines
------------------ ------------------
Virt Virt
M: Xiaojuan Yang <yangxiaojuan@loongson.cn>
M: Song Gao <gaosong@loongson.cn> M: Song Gao <gaosong@loongson.cn>
S: Maintained S: Maintained
F: docs/system/loongarch/virt.rst F: docs/system/loongarch/virt.rst

2
hw/loongarch/Kconfig
View File

@ -5,9 +5,7 @@ config LOONGARCH_VIRT
imply VIRTIO_VGA imply VIRTIO_VGA
imply PCI_DEVICES imply PCI_DEVICES
imply NVDIMM imply NVDIMM
select ISA_BUS
select SERIAL select SERIAL
select SERIAL_ISA
select VIRTIO_PCI select VIRTIO_PCI
select PLATFORM_BUS select PLATFORM_BUS
select LOONGARCH_IPI select LOONGARCH_IPI

103
hw/loongarch/virt.c
View File

@ -47,6 +47,13 @@
#include "qemu/error-report.h" #include "qemu/error-report.h"
struct loaderparams {
uint64_t ram_size;
const char *kernel_filename;
const char *kernel_cmdline;
const char *initrd_filename;
};
static void virt_flash_create(LoongArchMachineState *lams) static void virt_flash_create(LoongArchMachineState *lams)
{ {
DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
@ -301,10 +308,6 @@ static void fdt_add_memory_node(MachineState *ms,
g_free(nodename); g_free(nodename);
} }
#define PM_BASE 0x10080000
#define PM_SIZE 0x100
#define PM_CTRL 0x10
static void virt_build_smbios(LoongArchMachineState *lams) static void virt_build_smbios(LoongArchMachineState *lams)
{ {
MachineState *ms = MACHINE(lams); MachineState *ms = MACHINE(lams);
@ -373,62 +376,17 @@ static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type)
memmap_entries++; memmap_entries++;
} }
/*
* This is a placeholder for missing ACPI,
* and will eventually be replaced.
*/
static uint64_t loongarch_virt_pm_read(void *opaque, hwaddr addr, unsigned size)
{
return 0;
}
static void loongarch_virt_pm_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
if (addr != PM_CTRL) {
return;
}
switch (val) {
case 0x00:
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
return;
case 0xff:
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
return;
default:
return;
}
}
static const MemoryRegionOps loongarch_virt_pm_ops = {
.read = loongarch_virt_pm_read,
.write = loongarch_virt_pm_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 1,
.max_access_size = 1
}
};
static struct _loaderparams {
uint64_t ram_size;
const char *kernel_filename;
const char *kernel_cmdline;
const char *initrd_filename;
} loaderparams;
static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr) static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr)
{ {
return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS); return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS);
} }
static int64_t load_kernel_info(void) static int64_t load_kernel_info(const struct loaderparams *loaderparams)
{ {
uint64_t kernel_entry, kernel_low, kernel_high; uint64_t kernel_entry, kernel_low, kernel_high;
ssize_t kernel_size; ssize_t kernel_size;
kernel_size = load_elf(loaderparams.kernel_filename, NULL, kernel_size = load_elf(loaderparams->kernel_filename, NULL,
cpu_loongarch_virt_to_phys, NULL, cpu_loongarch_virt_to_phys, NULL,
&kernel_entry, &kernel_low, &kernel_entry, &kernel_low,
&kernel_high, NULL, 0, &kernel_high, NULL, 0,
@ -436,7 +394,7 @@ static int64_t load_kernel_info(void)
if (kernel_size < 0) { if (kernel_size < 0) {
error_report("could not load kernel '%s': %s", error_report("could not load kernel '%s': %s",
loaderparams.kernel_filename, loaderparams->kernel_filename,
load_elf_strerror(kernel_size)); load_elf_strerror(kernel_size));
exit(1); exit(1);
} }
@ -500,7 +458,7 @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
SysBusDevice *d; SysBusDevice *d;
PCIBus *pci_bus; PCIBus *pci_bus;
MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg;
MemoryRegion *mmio_alias, *mmio_reg, *pm_mem; MemoryRegion *mmio_alias, *mmio_reg;
int i; int i;
gpex_dev = qdev_new(TYPE_GPEX_HOST); gpex_dev = qdev_new(TYPE_GPEX_HOST);
@ -560,10 +518,6 @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
VIRT_RTC_IRQ - VIRT_GSI_BASE)); VIRT_RTC_IRQ - VIRT_GSI_BASE));
fdt_add_rtc_node(lams); fdt_add_rtc_node(lams);
pm_mem = g_new(MemoryRegion, 1);
memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops,
NULL, "loongarch_virt_pm", PM_SIZE);
memory_region_add_subregion(get_system_memory(), PM_BASE, pm_mem);
/* acpi ged */ /* acpi ged */
lams->acpi_ged = create_acpi_ged(pch_pic, lams); lams->acpi_ged = create_acpi_ged(pch_pic, lams);
/* platform bus */ /* platform bus */
@ -728,7 +682,8 @@ static void reset_load_elf(void *opaque)
} }
} }
static void fw_cfg_add_kernel_info(FWCfgState *fw_cfg) static void fw_cfg_add_kernel_info(const struct loaderparams *loaderparams,
FWCfgState *fw_cfg)
{ {
/* /*
* Expose the kernel, the command line, and the initrd in fw_cfg. * Expose the kernel, the command line, and the initrd in fw_cfg.
@ -737,36 +692,38 @@ static void fw_cfg_add_kernel_info(FWCfgState *fw_cfg)
*/ */
load_image_to_fw_cfg(fw_cfg, load_image_to_fw_cfg(fw_cfg,
FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA,
loaderparams.kernel_filename, loaderparams->kernel_filename,
false); false);
if (loaderparams.initrd_filename) { if (loaderparams->initrd_filename) {
load_image_to_fw_cfg(fw_cfg, load_image_to_fw_cfg(fw_cfg,
FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA,
loaderparams.initrd_filename, false); loaderparams->initrd_filename, false);
} }
if (loaderparams.kernel_cmdline) { if (loaderparams->kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
strlen(loaderparams.kernel_cmdline) + 1); strlen(loaderparams->kernel_cmdline) + 1);
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
loaderparams.kernel_cmdline); loaderparams->kernel_cmdline);
} }
} }
static void loongarch_firmware_boot(LoongArchMachineState *lams) static void loongarch_firmware_boot(LoongArchMachineState *lams,
const struct loaderparams *loaderparams)
{ {
fw_cfg_add_kernel_info(lams->fw_cfg); fw_cfg_add_kernel_info(loaderparams, lams->fw_cfg);
} }
static void loongarch_direct_kernel_boot(LoongArchMachineState *lams) static void loongarch_direct_kernel_boot(LoongArchMachineState *lams,
const struct loaderparams *loaderparams)
{ {
MachineState *machine = MACHINE(lams); MachineState *machine = MACHINE(lams);
int64_t kernel_addr = 0; int64_t kernel_addr = 0;
LoongArchCPU *lacpu; LoongArchCPU *lacpu;
int i; int i;
kernel_addr = load_kernel_info(); kernel_addr = load_kernel_info(loaderparams);
if (!machine->firmware) { if (!machine->firmware) {
for (i = 0; i < machine->smp.cpus; i++) { for (i = 0; i < machine->smp.cpus; i++) {
lacpu = LOONGARCH_CPU(qemu_get_cpu(i)); lacpu = LOONGARCH_CPU(qemu_get_cpu(i));
@ -793,6 +750,7 @@ static void loongarch_init(MachineState *machine)
MachineClass *mc = MACHINE_GET_CLASS(machine); MachineClass *mc = MACHINE_GET_CLASS(machine);
CPUState *cpu; CPUState *cpu;
char *ramName = NULL; char *ramName = NULL;
struct loaderparams loaderparams = { };
if (!cpu_model) { if (!cpu_model) {
cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
@ -874,11 +832,6 @@ static void loongarch_init(MachineState *machine)
machine_memory_devices_init(machine, device_mem_base, device_mem_size); machine_memory_devices_init(machine, device_mem_base, device_mem_size);
} }
/* Add isa io region */
memory_region_init_alias(&lams->isa_io, NULL, "isa-io",
get_system_io(), 0, VIRT_ISA_IO_SIZE);
memory_region_add_subregion(address_space_mem, VIRT_ISA_IO_BASE,
&lams->isa_io);
/* load the BIOS image. */ /* load the BIOS image. */
loongarch_firmware_init(lams); loongarch_firmware_init(lams);
@ -898,9 +851,9 @@ static void loongarch_init(MachineState *machine)
/* load the kernel. */ /* load the kernel. */
if (loaderparams.kernel_filename) { if (loaderparams.kernel_filename) {
if (lams->bios_loaded) { if (lams->bios_loaded) {
loongarch_firmware_boot(lams); loongarch_firmware_boot(lams, &loaderparams);
} else { } else {
loongarch_direct_kernel_boot(lams); loongarch_direct_kernel_boot(lams, &loaderparams);
} }
} }
fdt_add_flash_node(lams); fdt_add_flash_node(lams);

3
include/hw/loongarch/virt.h
View File

@ -16,8 +16,6 @@
#define LOONGARCH_MAX_CPUS 256 #define LOONGARCH_MAX_CPUS 256
#define VIRT_ISA_IO_BASE 0x18000000UL
#define VIRT_ISA_IO_SIZE 0x0004000
#define VIRT_FWCFG_BASE 0x1e020000UL #define VIRT_FWCFG_BASE 0x1e020000UL
#define VIRT_BIOS_BASE 0x1c000000UL #define VIRT_BIOS_BASE 0x1c000000UL
#define VIRT_BIOS_SIZE (4 * MiB) #define VIRT_BIOS_SIZE (4 * MiB)
@ -38,7 +36,6 @@ struct LoongArchMachineState {
MemoryRegion lowmem; MemoryRegion lowmem;
MemoryRegion highmem; MemoryRegion highmem;
MemoryRegion isa_io;
MemoryRegion bios; MemoryRegion bios;
bool bios_loaded; bool bios_loaded;
/* State for other subsystems/APIs: */ /* State for other subsystems/APIs: */

4
target/loongarch/cpu.h
View File

@ -458,11 +458,11 @@ static inline void set_pc(CPULoongArchState *env, uint64_t value)
* LoongArch CPUs hardware flags. * LoongArch CPUs hardware flags.
*/ */
#define HW_FLAGS_PLV_MASK R_CSR_CRMD_PLV_MASK /* 0x03 */ #define HW_FLAGS_PLV_MASK R_CSR_CRMD_PLV_MASK /* 0x03 */
#define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */
#define HW_FLAGS_EUEN_FPE 0x04 #define HW_FLAGS_EUEN_FPE 0x04
#define HW_FLAGS_EUEN_SXE 0x08 #define HW_FLAGS_EUEN_SXE 0x08
#define HW_FLAGS_EUEN_ASXE 0x10 #define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */
#define HW_FLAGS_VA32 0x20 #define HW_FLAGS_VA32 0x20
#define HW_FLAGS_EUEN_ASXE 0x40
static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *flags) uint64_t *cs_base, uint32_t *flags)

7
target/loongarch/disas.c
View File

@ -190,6 +190,12 @@ static void output_hint_r_i(DisasContext *ctx, arg_hint_r_i *a,
output(ctx, mnemonic, "%d, r%d, %d", a->hint, a->rj, a->imm); output(ctx, mnemonic, "%d, r%d, %d", a->hint, a->rj, a->imm);
} }
static void output_hint_rr(DisasContext *ctx, arg_hint_rr *a,
const char *mnemonic)
{
output(ctx, mnemonic, "%d, r%d, r%d", a->hint, a->rj, a->rk);
}
static void output_i(DisasContext *ctx, arg_i *a, const char *mnemonic) static void output_i(DisasContext *ctx, arg_i *a, const char *mnemonic)
{ {
output(ctx, mnemonic, "%d", a->imm); output(ctx, mnemonic, "%d", a->imm);
@ -549,6 +555,7 @@ INSN(ld_bu, rr_i)
INSN(ld_hu, rr_i) INSN(ld_hu, rr_i)
INSN(ld_wu, rr_i) INSN(ld_wu, rr_i)
INSN(preld, hint_r_i) INSN(preld, hint_r_i)
INSN(preldx, hint_rr)
INSN(fld_s, fr_i) INSN(fld_s, fr_i)
INSN(fst_s, fr_i) INSN(fst_s, fr_i)
INSN(fld_d, fr_i) INSN(fld_d, fr_i)

5
target/loongarch/insn_trans/trans_memory.c.inc
View File

@ -110,6 +110,11 @@ static bool trans_preld(DisasContext *ctx, arg_preld *a)
return true; return true;
} }
static bool trans_preldx(DisasContext *ctx, arg_preldx * a)
{
return true;
}
static bool trans_dbar(DisasContext *ctx, arg_dbar * a) static bool trans_dbar(DisasContext *ctx, arg_dbar * a)
{ {
tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);

3
target/loongarch/insns.decode
View File

@ -24,6 +24,7 @@
&rrr rd rj rk &rrr rd rj rk
&rr_i rd rj imm &rr_i rd rj imm
&hint_r_i hint rj imm &hint_r_i hint rj imm
&hint_rr hint rj rk
&rrr_sa rd rj rk sa &rrr_sa rd rj rk sa
&rr_ms_ls rd rj ms ls &rr_ms_ls rd rj ms ls
&ff fd fj &ff fd fj
@ -69,6 +70,7 @@
@rr_i16 .... .. imm:s16 rj:5 rd:5 &rr_i @rr_i16 .... .. imm:s16 rj:5 rd:5 &rr_i
@rr_i16s2 .... .. ................ rj:5 rd:5 &rr_i imm=%offs16 @rr_i16s2 .... .. ................ rj:5 rd:5 &rr_i imm=%offs16
@hint_r_i12 .... ...... imm:s12 rj:5 hint:5 &hint_r_i @hint_r_i12 .... ...... imm:s12 rj:5 hint:5 &hint_r_i
@hint_rr .... ........ ..... rk:5 rj:5 hint:5 &hint_rr
@rrr_sa2p1 .... ........ ... .. rk:5 rj:5 rd:5 &rrr_sa sa=%sa2p1 @rrr_sa2p1 .... ........ ... .. rk:5 rj:5 rd:5 &rrr_sa sa=%sa2p1
@rrr_sa2 .... ........ ... sa:2 rk:5 rj:5 rd:5 &rrr_sa @rrr_sa2 .... ........ ... sa:2 rk:5 rj:5 rd:5 &rrr_sa
@rrr_sa3 .... ........ .. sa:3 rk:5 rj:5 rd:5 &rrr_sa @rrr_sa3 .... ........ .. sa:3 rk:5 rj:5 rd:5 &rrr_sa
@ -228,6 +230,7 @@ ldx_bu 0011 10000010 00000 ..... ..... ..... @rrr
ldx_hu 0011 10000010 01000 ..... ..... ..... @rrr ldx_hu 0011 10000010 01000 ..... ..... ..... @rrr
ldx_wu 0011 10000010 10000 ..... ..... ..... @rrr ldx_wu 0011 10000010 10000 ..... ..... ..... @rrr
preld 0010 101011 ............ ..... ..... @hint_r_i12 preld 0010 101011 ............ ..... ..... @hint_r_i12
preldx 0011 10000010 11000 ..... ..... ..... @hint_rr
dbar 0011 10000111 00100 ............... @i15 dbar 0011 10000111 00100 ............... @i15
ibar 0011 10000111 00101 ............... @i15 ibar 0011 10000111 00101 ............... @i15
ldptr_w 0010 0100 .............. ..... ..... @rr_i14s2 ldptr_w 0010 0100 .............. ..... ..... @rr_i14s2

7
tests/tcg/loongarch64/system/boot.S
View File

@ -21,9 +21,10 @@ _start:
.align 16 .align 16
_exit: _exit:
2: /* QEMU ACPI poweroff */ 2: /* QEMU ACPI poweroff */
li.w t0, 0xff li.w t0, 0x34
li.w t1, 0x10080010 li.w t1, 0x100e001c
st.w t0, t1, 0 st.b t0, t1, 0
idle 0 idle 0
bl 2b bl 2b