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pull-loongarch-20240509

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Merge tag 'pull-loongarch-20240509' of https://gitlab.com/gaosong/qemu into staging

pull-loongarch-20240509

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* tag 'pull-loongarch-20240509' of https://gitlab.com/gaosong/qemu:
  target/loongarch: Put cpucfg operation before CSR register
  target/loongarch: Add TCG macro in structure CPUArchState
  hw/loongarch: Refine default numa id calculation

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-05-09 10:11:39 +02:00
commit 937e2cb759
6 changed files with 64 additions and 29 deletions
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11
hw/loongarch/virt.c
View File

@ -1182,15 +1182,14 @@ static CpuInstanceProperties virt_cpu_index_to_props(MachineState *ms,
static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
{
int64_t nidx = 0;
int64_t socket_id;
if (ms->numa_state->num_nodes) {
nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes);
if (ms->numa_state->num_nodes <= nidx) {
nidx = ms->numa_state->num_nodes - 1;
}
socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
return socket_id % ms->numa_state->num_nodes;
} else {
return 0;
}
return nidx;
}
static void virt_class_init(ObjectClass *oc, void *data)

7
target/loongarch/cpu.c
View File

@ -505,7 +505,9 @@ static void loongarch_cpu_reset_hold(Object *obj, ResetType type)
lacc->parent_phases.hold(obj, type);
}
#ifdef CONFIG_TCG
env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3;
#endif
env->fcsr0 = 0x0;
int n;
@ -550,7 +552,9 @@ static void loongarch_cpu_reset_hold(Object *obj, ResetType type)
#ifndef CONFIG_USER_ONLY
env->pc = 0x1c000000;
#ifdef CONFIG_TCG
memset(env->tlb, 0, sizeof(env->tlb));
#endif
if (kvm_enabled()) {
kvm_arch_reset_vcpu(env);
}
@ -686,8 +690,7 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
int i;
qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
qemu_fprintf(f, " FCSR0 0x%08x fp_status 0x%02x\n", env->fcsr0,
get_float_exception_flags(&env->fp_status));
qemu_fprintf(f, " FCSR0 0x%08x\n", env->fcsr0);
/* gpr */
for (i = 0; i < 32; i++) {

16
target/loongarch/cpu.h
View File

@ -270,6 +270,7 @@ union fpr_t {
VReg vreg;
};
#ifdef CONFIG_TCG
struct LoongArchTLB {
uint64_t tlb_misc;
/* Fields corresponding to CSR_TLBELO0/1 */
@ -277,23 +278,18 @@ struct LoongArchTLB {
uint64_t tlb_entry1;
};
typedef struct LoongArchTLB LoongArchTLB;
#endif
typedef struct CPUArchState {
uint64_t gpr[32];
uint64_t pc;
fpr_t fpr[32];
float_status fp_status;
bool cf[8];
uint32_t fcsr0;
uint32_t fcsr0_mask;
uint32_t cpucfg[21];
uint64_t lladdr; /* LL virtual address compared against SC */
uint64_t llval;
/* LoongArch CSRs */
uint64_t CSR_CRMD;
uint64_t CSR_PRMD;
@ -350,8 +346,16 @@ typedef struct CPUArchState {
uint64_t CSR_DERA;
uint64_t CSR_DSAVE;
#ifdef CONFIG_TCG
float_status fp_status;
uint32_t fcsr0_mask;
uint64_t lladdr; /* LL virtual address compared against SC */
uint64_t llval;
#endif
#ifndef CONFIG_USER_ONLY
#ifdef CONFIG_TCG
LoongArchTLB tlb[LOONGARCH_TLB_MAX];
#endif
AddressSpace *address_space_iocsr;
bool load_elf;

9
target/loongarch/cpu_helper.c
View File

@ -11,6 +11,7 @@
#include "internals.h"
#include "cpu-csr.h"
#ifdef CONFIG_TCG
static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
int *prot, target_ulong address,
int access_type, int index, int mmu_idx)
@ -154,6 +155,14 @@ static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
return TLBRET_NOMATCH;
}
#else
static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
int *prot, target_ulong address,
MMUAccessType access_type, int mmu_idx)
{
return TLBRET_NOMATCH;
}
#endif
static hwaddr dmw_va2pa(CPULoongArchState *env, target_ulong va,
target_ulong dmw)

20
target/loongarch/kvm/kvm.c
View File

@ -587,6 +587,11 @@ int kvm_arch_get_registers(CPUState *cs)
return ret;
}
ret = kvm_loongarch_get_cpucfg(cs);
if (ret) {
return ret;
}
ret = kvm_loongarch_get_csr(cs);
if (ret) {
return ret;
@ -598,11 +603,6 @@ int kvm_arch_get_registers(CPUState *cs)
}
ret = kvm_loongarch_get_mpstate(cs);
if (ret) {
return ret;
}
ret = kvm_loongarch_get_cpucfg(cs);
return ret;
}
@ -615,6 +615,11 @@ int kvm_arch_put_registers(CPUState *cs, int level)
return ret;
}
ret = kvm_loongarch_put_cpucfg(cs);
if (ret) {
return ret;
}
ret = kvm_loongarch_put_csr(cs, level);
if (ret) {
return ret;
@ -626,11 +631,6 @@ int kvm_arch_put_registers(CPUState *cs, int level)
}
ret = kvm_loongarch_put_mpstate(cs);
if (ret) {
return ret;
}
ret = kvm_loongarch_put_cpucfg(cs);
return ret;
}

30
target/loongarch/machine.c
View File

@ -8,6 +8,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "migration/cpu.h"
#include "sysemu/tcg.h"
#include "vec.h"
static const VMStateDescription vmstate_fpu_reg = {
@ -109,9 +110,15 @@ static const VMStateDescription vmstate_lasx = {
},
};
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
static bool tlb_needed(void *opaque)
{
return tcg_enabled();
}
/* TLB state */
const VMStateDescription vmstate_tlb = {
.name = "cpu/tlb",
static const VMStateDescription vmstate_tlb_entry = {
.name = "cpu/tlb_entry",
.version_id = 0,
.minimum_version_id = 0,
.fields = (const VMStateField[]) {
@ -122,6 +129,19 @@ const VMStateDescription vmstate_tlb = {
}
};
static const VMStateDescription vmstate_tlb = {
.name = "cpu/tlb",
.version_id = 0,
.minimum_version_id = 0,
.needed = tlb_needed,
.fields = (const VMStateField[]) {
VMSTATE_STRUCT_ARRAY(env.tlb, LoongArchCPU, LOONGARCH_TLB_MAX,
0, vmstate_tlb_entry, LoongArchTLB),
VMSTATE_END_OF_LIST()
}
};
#endif
/* LoongArch CPU state */
const VMStateDescription vmstate_loongarch_cpu = {
.name = "cpu",
@ -187,9 +207,6 @@ const VMStateDescription vmstate_loongarch_cpu = {
VMSTATE_UINT64(env.CSR_DBG, LoongArchCPU),
VMSTATE_UINT64(env.CSR_DERA, LoongArchCPU),
VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU),
/* TLB */
VMSTATE_STRUCT_ARRAY(env.tlb, LoongArchCPU, LOONGARCH_TLB_MAX,
0, vmstate_tlb, LoongArchTLB),
VMSTATE_END_OF_LIST()
},
@ -197,6 +214,9 @@ const VMStateDescription vmstate_loongarch_cpu = {
&vmstate_fpu,
&vmstate_lsx,
&vmstate_lasx,
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
&vmstate_tlb,
#endif
NULL
}
};