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target/xtensa: Use env_cpu, env_archcpu

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Cleanup in the boilerplate that each target must define.
Replace xtensa_env_get_cpu with env_archcpu.  The combination
CPU(xtensa_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.

Move cpu_get_tb_cpu_state below the include of "exec/cpu-all.h"
so that the definition of env_cpu is available.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2019-03-22 19:52:17 -07:00
parent 31266e68d2
commit 92fddfbd17
8 changed files with 22 additions and 33 deletions
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2
hw/xtensa/pic_cpu.c
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@ -33,7 +33,7 @@
void check_interrupts(CPUXtensaState *env)
{
CPUState *cs = CPU(xtensa_env_get_cpu(env));
CPUState *cs = env_cpu(env);
int minlevel = xtensa_get_cintlevel(env);
uint32_t int_set_enabled = env->sregs[INTSET] & env->sregs[INTENABLE];
int level;

2
linux-user/xtensa/cpu_loop.c
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@ -123,7 +123,7 @@ static void xtensa_underflow12(CPUXtensaState *env)
void cpu_loop(CPUXtensaState *env)
{
CPUState *cs = CPU(xtensa_env_get_cpu(env));
CPUState *cs = env_cpu(env);
target_siginfo_t info;
abi_ulong ret;
int trapnr;

17
target/xtensa/cpu.h
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@ -559,11 +559,6 @@ struct XtensaCPU {
CPUXtensaState env;
};
static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
{
return container_of(env, XtensaCPU, env);
}
#define ENV_OFFSET offsetof(XtensaCPU, env)
@ -724,10 +719,15 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
#define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000
#define XTENSA_CSBASE_LBEG_OFF_SHIFT 16
typedef CPUXtensaState CPUArchState;
typedef XtensaCPU ArchCPU;
#include "exec/cpu-all.h"
static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
{
CPUState *cs = CPU(xtensa_env_get_cpu(env));
CPUState *cs = env_cpu(env);
*pc = env->pc;
*cs_base = 0;
@ -797,9 +797,4 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
}
}
typedef CPUXtensaState CPUArchState;
typedef XtensaCPU ArchCPU;
#include "exec/cpu-all.h"
#endif

4
target/xtensa/dbg_helper.c
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@ -71,7 +71,7 @@ void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
uint32_t dbreakc)
{
CPUState *cs = CPU(xtensa_env_get_cpu(env));
CPUState *cs = env_cpu(env);
int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
uint32_t mask = dbreakc | ~DBREAKC_MASK;
@ -118,7 +118,7 @@ void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v)
set_dbreak(env, i, env->sregs[DBREAKA + i], v);
} else {
if (env->cpu_watchpoint[i]) {
CPUState *cs = CPU(xtensa_env_get_cpu(env));
CPUState *cs = env_cpu(env);
cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
env->cpu_watchpoint[i] = NULL;

9
target/xtensa/exc_helper.c
View File

@ -34,7 +34,7 @@
void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
{
CPUState *cs = CPU(xtensa_env_get_cpu(env));
CPUState *cs = env_cpu(env);
cs->exception_index = excp;
if (excp == EXCP_YIELD) {
@ -100,7 +100,7 @@ void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
{
CPUState *cpu;
CPUState *cpu = env_cpu(env);
env->pc = pc;
env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |
@ -111,11 +111,10 @@ void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
qemu_mutex_unlock_iothread();
if (env->pending_irq_level) {
cpu_loop_exit(CPU(xtensa_env_get_cpu(env)));
cpu_loop_exit(cpu);
return;
}
cpu = CPU(xtensa_env_get_cpu(env));
cpu->halted = 1;
HELPER(exception)(env, EXCP_HLT);
}
@ -165,7 +164,7 @@ static void handle_interrupt(CPUXtensaState *env)
(env->config->level_mask[level] &
env->sregs[INTSET] &
env->sregs[INTENABLE])) {
CPUState *cs = CPU(xtensa_env_get_cpu(env));
CPUState *cs = env_cpu(env);
if (level > 1) {
env->sregs[EPC1 + level - 1] = env->pc;

2
target/xtensa/helper.c
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@ -324,7 +324,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
void xtensa_runstall(CPUXtensaState *env, bool runstall)
{
CPUState *cpu = CPU(xtensa_env_get_cpu(env));
CPUState *cpu = env_cpu(env);
env->runstall = runstall;
cpu->halted = runstall;

17
target/xtensa/mmu_helper.c
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@ -71,12 +71,10 @@ void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr)
void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
{
XtensaCPU *cpu = xtensa_env_get_cpu(env);
v = (v & 0xffffff00) | 0x1;
if (v != env->sregs[RASID]) {
env->sregs[RASID] = v;
tlb_flush(CPU(cpu));
tlb_flush(env_cpu(env));
}
}
@ -276,8 +274,7 @@ static void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
unsigned wi, unsigned ei,
uint32_t vpn, uint32_t pte)
{
XtensaCPU *cpu = xtensa_env_get_cpu(env);
CPUState *cs = CPU(cpu);
CPUState *cs = env_cpu(env);
xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
@ -503,7 +500,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
uint32_t wi;
xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
if (entry->variable && entry->asid) {
tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr);
tlb_flush_page(env_cpu(env), entry->vaddr);
entry->asid = 0;
}
}
@ -844,7 +841,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
{
CPUState *cs = CPU(xtensa_env_get_cpu(env));
CPUState *cs = env_cpu(env);
uint32_t paddr;
uint32_t page_size;
unsigned access;
@ -924,13 +921,11 @@ static int xtensa_mpu_lookup(const xtensa_mpu_entry *entry, unsigned n,
void HELPER(wsr_mpuenb)(CPUXtensaState *env, uint32_t v)
{
XtensaCPU *cpu = xtensa_env_get_cpu(env);
v &= (2u << (env->config->n_mpu_fg_segments - 1)) - 1;
if (v != env->sregs[MPUENB]) {
env->sregs[MPUENB] = v;
tlb_flush(CPU(cpu));
tlb_flush(env_cpu(env));
}
}
@ -942,7 +937,7 @@ void HELPER(wptlb)(CPUXtensaState *env, uint32_t p, uint32_t v)
env->mpu_fg[segment].vaddr = v & -env->config->mpu_align;
env->mpu_fg[segment].attr = p & XTENSA_MPU_ATTR_MASK;
env->sregs[MPUENB] = deposit32(env->sregs[MPUENB], segment, 1, v);
tlb_flush(CPU(xtensa_env_get_cpu(env)));
tlb_flush(env_cpu(env));
}
}

2
target/xtensa/xtensa-semi.c
View File

@ -197,7 +197,7 @@ void xtensa_sim_open_console(Chardev *chr)
void HELPER(simcall)(CPUXtensaState *env)
{
CPUState *cs = CPU(xtensa_env_get_cpu(env));
CPUState *cs = env_cpu(env);
uint32_t *regs = env->regs;
switch (regs[2]) {