target/sh4: return result of fcmp using TCG
Since that the T bit of the SR register is mapped using a TGC global, it's better to return the value through TCG than writing it directly. It allows to declare the helpers with the flag TCG_CALL_NO_WG. Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170702202814.27793-5-aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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@ -21,10 +21,10 @@ DEF_HELPER_FLAGS_3(fadd_DT, TCG_CALL_NO_WG, f64, env, f64, f64)
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DEF_HELPER_FLAGS_2(fcnvsd_FT_DT, TCG_CALL_NO_WG, f64, env, f32)
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DEF_HELPER_FLAGS_2(fcnvds_DT_FT, TCG_CALL_NO_WG, f32, env, f64)
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DEF_HELPER_3(fcmp_eq_FT, void, env, f32, f32)
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DEF_HELPER_3(fcmp_eq_DT, void, env, f64, f64)
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DEF_HELPER_3(fcmp_gt_FT, void, env, f32, f32)
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DEF_HELPER_3(fcmp_gt_DT, void, env, f64, f64)
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DEF_HELPER_FLAGS_3(fcmp_eq_FT, TCG_CALL_NO_WG, i32, env, f32, f32)
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DEF_HELPER_FLAGS_3(fcmp_eq_DT, TCG_CALL_NO_WG, i32, env, f64, f64)
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DEF_HELPER_FLAGS_3(fcmp_gt_FT, TCG_CALL_NO_WG, i32, env, f32, f32)
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DEF_HELPER_FLAGS_3(fcmp_gt_DT, TCG_CALL_NO_WG, i32, env, f64, f64)
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DEF_HELPER_FLAGS_3(fdiv_FT, TCG_CALL_NO_WG, f32, env, f32, f32)
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DEF_HELPER_FLAGS_3(fdiv_DT, TCG_CALL_NO_WG, f64, env, f64, f64)
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DEF_HELPER_FLAGS_2(float_FT, TCG_CALL_NO_WG, f32, env, i32)
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@ -268,44 +268,44 @@ float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1)
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return t0;
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}
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void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
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uint32_t helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
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{
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int relation;
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set_float_exception_flags(0, &env->fp_status);
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relation = float32_compare(t0, t1, &env->fp_status);
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update_fpscr(env, GETPC());
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env->sr_t = (relation == float_relation_equal);
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return relation == float_relation_equal;
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}
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void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
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uint32_t helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
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{
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int relation;
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set_float_exception_flags(0, &env->fp_status);
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relation = float64_compare(t0, t1, &env->fp_status);
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update_fpscr(env, GETPC());
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env->sr_t = (relation == float_relation_equal);
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return relation == float_relation_equal;
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}
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void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
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uint32_t helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
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{
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int relation;
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set_float_exception_flags(0, &env->fp_status);
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relation = float32_compare(t0, t1, &env->fp_status);
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update_fpscr(env, GETPC());
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env->sr_t = (relation == float_relation_greater);
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return relation == float_relation_greater;
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}
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void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
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uint32_t helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
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{
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int relation;
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set_float_exception_flags(0, &env->fp_status);
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relation = float64_compare(t0, t1, &env->fp_status);
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update_fpscr(env, GETPC());
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env->sr_t = (relation == float_relation_greater);
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return relation == float_relation_greater;
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}
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float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0)
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@ -1077,10 +1077,10 @@ static void _decode_opc(DisasContext * ctx)
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gen_helper_fdiv_DT(fp0, cpu_env, fp0, fp1);
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break;
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case 0xf004: /* fcmp/eq Rm,Rn */
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gen_helper_fcmp_eq_DT(cpu_env, fp0, fp1);
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gen_helper_fcmp_eq_DT(cpu_sr_t, cpu_env, fp0, fp1);
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return;
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case 0xf005: /* fcmp/gt Rm,Rn */
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gen_helper_fcmp_gt_DT(cpu_env, fp0, fp1);
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gen_helper_fcmp_gt_DT(cpu_sr_t, cpu_env, fp0, fp1);
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return;
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}
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gen_store_fpr64(fp0, DREG(B11_8));
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@ -1109,11 +1109,13 @@ static void _decode_opc(DisasContext * ctx)
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cpu_fregs[FREG(B7_4)]);
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break;
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case 0xf004: /* fcmp/eq Rm,Rn */
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gen_helper_fcmp_eq_FT(cpu_env, cpu_fregs[FREG(B11_8)],
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gen_helper_fcmp_eq_FT(cpu_sr_t, cpu_env,
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cpu_fregs[FREG(B11_8)],
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cpu_fregs[FREG(B7_4)]);
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return;
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case 0xf005: /* fcmp/gt Rm,Rn */
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gen_helper_fcmp_gt_FT(cpu_env, cpu_fregs[FREG(B11_8)],
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gen_helper_fcmp_gt_FT(cpu_sr_t, cpu_env,
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cpu_fregs[FREG(B11_8)],
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cpu_fregs[FREG(B7_4)]);
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return;
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}
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