tcg/riscv: Add the prologue generation and register the JIT
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <c4d023127967a0217d8d1eabdf5de6c0e8f8c228.1545246859.git.alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Alistair Francis
Richard Henderson
parent
bdf503819e
commit
92c041c59b
@ -1805,3 +1805,114 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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return NULL;
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return NULL;
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}
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}
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}
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}
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static const int tcg_target_callee_save_regs[] = {
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TCG_REG_S0, /* used for the global env (TCG_AREG0) */
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TCG_REG_S1,
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TCG_REG_S2,
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TCG_REG_S3,
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TCG_REG_S4,
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TCG_REG_S5,
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TCG_REG_S6,
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TCG_REG_S7,
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TCG_REG_S8,
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TCG_REG_S9,
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TCG_REG_S10,
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TCG_REG_S11,
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TCG_REG_RA, /* should be last for ABI compliance */
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};
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/* Stack frame parameters. */
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#define REG_SIZE (TCG_TARGET_REG_BITS / 8)
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#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
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#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
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#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
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+ TCG_TARGET_STACK_ALIGN - 1) \
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& -TCG_TARGET_STACK_ALIGN)
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#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
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/* We're expecting to be able to use an immediate for frame allocation. */
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QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff);
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/* Generate global QEMU prologue and epilogue code */
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static void tcg_target_qemu_prologue(TCGContext *s)
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{
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int i;
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tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
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/* TB prologue */
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tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
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for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
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tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
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TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
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}
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#if !defined(CONFIG_SOFTMMU)
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
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tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
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#endif
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/* Call generated code */
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tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
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tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0);
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/* Return path for goto_ptr. Set return value to 0 */
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s->code_gen_epilogue = s->code_ptr;
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tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO);
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/* TB epilogue */
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tb_ret_addr = s->code_ptr;
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for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
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tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
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TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
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}
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tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
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tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0);
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}
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typedef struct {
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DebugFrameHeader h;
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uint8_t fde_def_cfa[4];
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uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
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} DebugFrame;
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#define ELF_HOST_MACHINE EM_RISCV
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static const DebugFrame debug_frame = {
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.h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
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.h.cie.id = -1,
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.h.cie.version = 1,
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.h.cie.code_align = 1,
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.h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
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.h.cie.return_column = TCG_REG_RA,
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/* Total FDE size does not include the "len" member. */
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.h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
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.fde_def_cfa = {
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12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
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(FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
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(FRAME_SIZE >> 7)
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},
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.fde_reg_ofs = {
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0x80 + 9, 12, /* DW_CFA_offset, s1, -96 */
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0x80 + 18, 11, /* DW_CFA_offset, s2, -88 */
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0x80 + 19, 10, /* DW_CFA_offset, s3, -80 */
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0x80 + 20, 9, /* DW_CFA_offset, s4, -72 */
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0x80 + 21, 8, /* DW_CFA_offset, s5, -64 */
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0x80 + 22, 7, /* DW_CFA_offset, s6, -56 */
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0x80 + 23, 6, /* DW_CFA_offset, s7, -48 */
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0x80 + 24, 5, /* DW_CFA_offset, s8, -40 */
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0x80 + 25, 4, /* DW_CFA_offset, s9, -32 */
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0x80 + 26, 3, /* DW_CFA_offset, s10, -24 */
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0x80 + 27, 2, /* DW_CFA_offset, s11, -16 */
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0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */
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}
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};
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void tcg_register_jit(void *buf, size_t buf_size)
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{
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tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
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}
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