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omap_gpio: convert to memory API

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Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Avi Kivity 2011-11-24 14:32:34 +02:00
parent 7405165e26
commit 9244b42dea
1 changed files with 48 additions and 47 deletions
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95
hw/omap_gpio.c
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@ -37,6 +37,7 @@ struct omap_gpio_s {
struct omap_gpif_s { struct omap_gpif_s {
SysBusDevice busdev; SysBusDevice busdev;
MemoryRegion iomem;
int mpu_model; int mpu_model;
void *clk; void *clk;
struct omap_gpio_s omap1; struct omap_gpio_s omap1;
@ -60,11 +61,16 @@ static void omap_gpio_set(void *opaque, int line, int level)
} }
} }
static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr) static uint64_t omap_gpio_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{ {
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK; int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (offset) { switch (offset) {
case 0x00: /* DATA_INPUT */ case 0x00: /* DATA_INPUT */
return s->inputs & s->pins; return s->inputs & s->pins;
@ -94,13 +100,17 @@ static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr)
} }
static void omap_gpio_write(void *opaque, target_phys_addr_t addr, static void omap_gpio_write(void *opaque, target_phys_addr_t addr,
uint32_t value) uint64_t value, unsigned size)
{ {
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK; int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t diff; uint16_t diff;
int ln; int ln;
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
}
switch (offset) { switch (offset) {
case 0x00: /* DATA_INPUT */ case 0x00: /* DATA_INPUT */
OMAP_RO_REG(addr); OMAP_RO_REG(addr);
@ -156,16 +166,10 @@ static void omap_gpio_write(void *opaque, target_phys_addr_t addr,
} }
/* *Some* sources say the memory region is 32-bit. */ /* *Some* sources say the memory region is 32-bit. */
static CPUReadMemoryFunc * const omap_gpio_readfn[] = { static const MemoryRegionOps omap_gpio_ops = {
omap_badwidth_read16, .read = omap_gpio_read,
omap_gpio_read, .write = omap_gpio_write,
omap_badwidth_read16, .endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const omap_gpio_writefn[] = {
omap_badwidth_write16,
omap_gpio_write,
omap_badwidth_write16,
}; };
static void omap_gpio_reset(struct omap_gpio_s *s) static void omap_gpio_reset(struct omap_gpio_s *s)
@ -183,6 +187,7 @@ struct omap2_gpio_s {
qemu_irq irq[2]; qemu_irq irq[2];
qemu_irq wkup; qemu_irq wkup;
qemu_irq *handler; qemu_irq *handler;
MemoryRegion iomem;
uint8_t revision; uint8_t revision;
uint8_t config[2]; uint8_t config[2];
@ -200,6 +205,7 @@ struct omap2_gpio_s {
struct omap2_gpif_s { struct omap2_gpif_s {
SysBusDevice busdev; SysBusDevice busdev;
MemoryRegion iomem;
int mpu_model; int mpu_model;
void *iclk; void *iclk;
void *fclk[6]; void *fclk[6];
@ -563,16 +569,20 @@ static void omap2_gpio_module_writep(void *opaque, target_phys_addr_t addr,
} }
} }
static CPUReadMemoryFunc * const omap2_gpio_module_readfn[] = { static const MemoryRegionOps omap2_gpio_module_ops = {
omap2_gpio_module_readp, .old_mmio = {
omap2_gpio_module_readp, .read = {
omap2_gpio_module_read, omap2_gpio_module_readp,
}; omap2_gpio_module_readp,
omap2_gpio_module_read,
static CPUWriteMemoryFunc * const omap2_gpio_module_writefn[] = { },
omap2_gpio_module_writep, .write = {
omap2_gpio_module_writep, omap2_gpio_module_writep,
omap2_gpio_module_write, omap2_gpio_module_writep,
omap2_gpio_module_write,
},
},
.endianness = DEVICE_NATIVE_ENDIAN,
}; };
static void omap_gpif_reset(DeviceState *dev) static void omap_gpif_reset(DeviceState *dev)
@ -594,7 +604,8 @@ static void omap2_gpif_reset(DeviceState *dev)
s->gpo = 0; s->gpo = 0;
} }
static uint32_t omap2_gpif_top_read(void *opaque, target_phys_addr_t addr) static uint64_t omap2_gpif_top_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{ {
struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque; struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
@ -623,7 +634,7 @@ static uint32_t omap2_gpif_top_read(void *opaque, target_phys_addr_t addr)
} }
static void omap2_gpif_top_write(void *opaque, target_phys_addr_t addr, static void omap2_gpif_top_write(void *opaque, target_phys_addr_t addr,
uint32_t value) uint64_t value, unsigned size)
{ {
struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque; struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
@ -651,16 +662,10 @@ static void omap2_gpif_top_write(void *opaque, target_phys_addr_t addr,
} }
} }
static CPUReadMemoryFunc * const omap2_gpif_top_readfn[] = { static const MemoryRegionOps omap2_gpif_top_ops = {
omap2_gpif_top_read, .read = omap2_gpif_top_read,
omap2_gpif_top_read, .write = omap2_gpif_top_write,
omap2_gpif_top_read, .endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const omap2_gpif_top_writefn[] = {
omap2_gpif_top_write,
omap2_gpif_top_write,
omap2_gpif_top_write,
}; };
static int omap_gpio_init(SysBusDevice *dev) static int omap_gpio_init(SysBusDevice *dev)
@ -672,11 +677,9 @@ static int omap_gpio_init(SysBusDevice *dev)
qdev_init_gpio_in(&dev->qdev, omap_gpio_set, 16); qdev_init_gpio_in(&dev->qdev, omap_gpio_set, 16);
qdev_init_gpio_out(&dev->qdev, s->omap1.handler, 16); qdev_init_gpio_out(&dev->qdev, s->omap1.handler, 16);
sysbus_init_irq(dev, &s->omap1.irq); sysbus_init_irq(dev, &s->omap1.irq);
sysbus_init_mmio(dev, 0x1000, memory_region_init_io(&s->iomem, &omap_gpio_ops, &s->omap1,
cpu_register_io_memory(omap_gpio_readfn, "omap.gpio", 0x1000);
omap_gpio_writefn, sysbus_init_mmio_region(dev, &s->iomem);
&s->omap1,
DEVICE_NATIVE_ENDIAN));
return 0; return 0;
} }
@ -689,10 +692,9 @@ static int omap2_gpio_init(SysBusDevice *dev)
} }
if (s->mpu_model < omap3430) { if (s->mpu_model < omap3430) {
s->modulecount = (s->mpu_model < omap2430) ? 4 : 5; s->modulecount = (s->mpu_model < omap2430) ? 4 : 5;
sysbus_init_mmio(dev, 0x1000, memory_region_init_io(&s->iomem, &omap2_gpif_top_ops, s,
cpu_register_io_memory(omap2_gpif_top_readfn, "omap2.gpio", 0x1000);
omap2_gpif_top_writefn, s, sysbus_init_mmio_region(dev, &s->iomem);
DEVICE_NATIVE_ENDIAN));
} else { } else {
s->modulecount = 6; s->modulecount = 6;
} }
@ -710,10 +712,9 @@ static int omap2_gpio_init(SysBusDevice *dev)
sysbus_init_irq(dev, &m->irq[0]); /* mpu irq */ sysbus_init_irq(dev, &m->irq[0]); /* mpu irq */
sysbus_init_irq(dev, &m->irq[1]); /* dsp irq */ sysbus_init_irq(dev, &m->irq[1]); /* dsp irq */
sysbus_init_irq(dev, &m->wkup); sysbus_init_irq(dev, &m->wkup);
sysbus_init_mmio(dev, 0x1000, memory_region_init_io(&m->iomem, &omap2_gpio_module_ops, m,
cpu_register_io_memory(omap2_gpio_module_readfn, "omap.gpio-module", 0x1000);
omap2_gpio_module_writefn, sysbus_init_mmio_region(dev, &m->iomem);
m, DEVICE_NATIVE_ENDIAN));
} }
return 0; return 0;
} }