target/riscv: rvb: shift ones
Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-11-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -680,11 +680,15 @@ bset 0010100 .......... 001 ..... 0110011 @r
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bclr 0100100 .......... 001 ..... 0110011 @r
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binv 0110100 .......... 001 ..... 0110011 @r
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bext 0100100 .......... 101 ..... 0110011 @r
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slo 0010000 .......... 001 ..... 0110011 @r
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sro 0010000 .......... 101 ..... 0110011 @r
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bseti 00101. ........... 001 ..... 0010011 @sh
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bclri 01001. ........... 001 ..... 0010011 @sh
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binvi 01101. ........... 001 ..... 0010011 @sh
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bexti 01001. ........... 101 ..... 0010011 @sh
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sloi 00100. ........... 001 ..... 0010011 @sh
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sroi 00100. ........... 101 ..... 0010011 @sh
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# *** RV64B Standard Extension (in addition to RV32B) ***
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clzw 0110000 00000 ..... 001 ..... 0011011 @r2
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@ -697,7 +701,11 @@ bsetw 0010100 .......... 001 ..... 0111011 @r
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bclrw 0100100 .......... 001 ..... 0111011 @r
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binvw 0110100 .......... 001 ..... 0111011 @r
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bextw 0100100 .......... 101 ..... 0111011 @r
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slow 0010000 .......... 001 ..... 0111011 @r
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srow 0010000 .......... 101 ..... 0111011 @r
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bsetiw 0010100 .......... 001 ..... 0011011 @sh5
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bclriw 0100100 .......... 001 ..... 0011011 @sh5
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binviw 0110100 .......... 001 ..... 0011011 @sh5
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sloiw 0010000 .......... 001 ..... 0011011 @sh5
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sroiw 0010000 .......... 101 ..... 0011011 @sh5
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@ -155,6 +155,30 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
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return gen_shifti(ctx, a, gen_bext);
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}
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static bool trans_slo(DisasContext *ctx, arg_slo *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_shift(ctx, a, gen_slo);
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}
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static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_shifti(ctx, a, gen_slo);
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}
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static bool trans_sro(DisasContext *ctx, arg_sro *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_shift(ctx, a, gen_sro);
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}
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static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_shifti(ctx, a, gen_sro);
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}
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static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
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{
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REQUIRE_64BIT(ctx);
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@ -238,3 +262,31 @@ static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
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REQUIRE_EXT(ctx, RVB);
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return gen_shiftw(ctx, a, gen_bext);
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}
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static bool trans_slow(DisasContext *ctx, arg_slow *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_EXT(ctx, RVB);
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return gen_shiftw(ctx, a, gen_slo);
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}
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static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_EXT(ctx, RVB);
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return gen_shiftiw(ctx, a, gen_slo);
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}
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static bool trans_srow(DisasContext *ctx, arg_srow *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_EXT(ctx, RVB);
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return gen_shiftw(ctx, a, gen_sro);
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}
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static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_EXT(ctx, RVB);
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return gen_shiftiw(ctx, a, gen_sro);
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}
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@ -613,6 +613,20 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
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tcg_gen_andi_tl(ret, ret, 1);
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}
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static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
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{
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tcg_gen_not_tl(ret, arg1);
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tcg_gen_shl_tl(ret, ret, arg2);
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tcg_gen_not_tl(ret, ret);
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}
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static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
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{
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tcg_gen_not_tl(ret, arg1);
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tcg_gen_shr_tl(ret, ret, arg2);
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tcg_gen_not_tl(ret, ret);
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}
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static void gen_ctzw(TCGv ret, TCGv arg1)
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{
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tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
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