tests/pflash-cfi02: Refactor to support testing multiple configurations
Introduce the FlashConfig structure, to be able to run the same set of tests on different flash models/configurations. Signed-off-by: Stephen Checkoway <stephen.checkoway@oberlin.edu> Message-Id: <20190426162624.55977-6-stephen.checkoway@oberlin.edu> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> [PMD: Extracted from bigger patch] Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
This commit is contained in:
Philippe Mathieu-Daudé
parent
6682bc1ee4
commit
91d0231213
@ -17,12 +17,18 @@
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*/
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#define MP_FLASH_SIZE_MAX (32 * 1024 * 1024)
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#define FLASH_SIZE (8 * 1024 * 1024)
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#define BASE_ADDR (0x100000000ULL - MP_FLASH_SIZE_MAX)
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#define FLASH_WIDTH 2
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#define CFI_ADDR (FLASH_WIDTH * 0x55)
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#define UNLOCK0_ADDR (FLASH_WIDTH * 0x555)
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#define UNLOCK1_ADDR (FLASH_WIDTH * 0x2AA)
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/* Use a newtype to keep flash addresses separate from byte addresses. */
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typedef struct {
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uint64_t addr;
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} faddr;
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#define FLASH_ADDR(x) ((faddr) { .addr = (x) })
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#define CFI_ADDR FLASH_ADDR(0x55)
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#define UNLOCK0_ADDR FLASH_ADDR(0x555)
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#define UNLOCK1_ADDR FLASH_ADDR(0x2AA)
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#define CFI_CMD 0x98
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#define UNLOCK0_CMD 0xAA
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@ -35,170 +41,313 @@
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#define UNLOCK_BYPASS_CMD 0x20
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#define UNLOCK_BYPASS_RESET_CMD 0x00
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typedef struct {
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int bank_width;
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QTestState *qtest;
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} FlashConfig;
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static char image_path[] = "/tmp/qtest.XXXXXX";
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static inline void flash_write(uint64_t byte_addr, uint16_t data)
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/*
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* The pflash implementation allows some parameters to be unspecified. We want
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* to test those configurations but we also need to know the real values in
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* our testing code. So after we launch qemu, we'll need a new FlashConfig
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* with the correct values filled in.
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*/
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static FlashConfig expand_config_defaults(const FlashConfig *c)
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{
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qtest_writew(global_qtest, BASE_ADDR + byte_addr, data);
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FlashConfig ret = *c;
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if (ret.bank_width == 0) {
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ret.bank_width = 2;
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}
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/* XXX: Limitations of test harness. */
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assert(ret.bank_width == 2);
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return ret;
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}
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static inline uint16_t flash_read(uint64_t byte_addr)
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/*
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* Return a bit mask suitable for extracting the least significant
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* status/query response from an interleaved response.
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*/
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static inline uint64_t device_mask(const FlashConfig *c)
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{
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return qtest_readw(global_qtest, BASE_ADDR + byte_addr);
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return (uint64_t)-1;
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}
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static void unlock(void)
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/*
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* Return a bit mask exactly as long as the bank_width.
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*/
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static inline uint64_t bank_mask(const FlashConfig *c)
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{
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flash_write(UNLOCK0_ADDR, UNLOCK0_CMD);
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flash_write(UNLOCK1_ADDR, UNLOCK1_CMD);
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if (c->bank_width == 8) {
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return (uint64_t)-1;
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}
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return (1ULL << (c->bank_width * 8)) - 1ULL;
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}
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static void reset(void)
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static inline void flash_write(const FlashConfig *c, uint64_t byte_addr,
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uint64_t data)
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{
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flash_write(0, RESET_CMD);
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}
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static void sector_erase(uint64_t byte_addr)
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{
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unlock();
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flash_write(UNLOCK0_ADDR, 0x80);
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unlock();
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flash_write(byte_addr, SECTOR_ERASE_CMD);
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}
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static void wait_for_completion(uint64_t byte_addr)
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{
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/* If DQ6 is toggling, step the clock and ensure the toggle stops. */
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if ((flash_read(byte_addr) & 0x40) ^ (flash_read(byte_addr) & 0x40)) {
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/* Wait for erase or program to finish. */
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clock_step_next();
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/* Ensure that DQ6 has stopped toggling. */
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g_assert_cmphex(flash_read(byte_addr), ==, flash_read(byte_addr));
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/* Sanity check our tests. */
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assert((data & ~bank_mask(c)) == 0);
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uint64_t addr = BASE_ADDR + byte_addr;
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switch (c->bank_width) {
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case 1:
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qtest_writeb(c->qtest, addr, data);
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break;
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case 2:
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qtest_writew(c->qtest, addr, data);
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break;
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case 4:
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qtest_writel(c->qtest, addr, data);
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break;
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case 8:
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qtest_writeq(c->qtest, addr, data);
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break;
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default:
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abort();
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}
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}
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static void bypass_program(uint64_t byte_addr, uint16_t data)
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static inline uint64_t flash_read(const FlashConfig *c, uint64_t byte_addr)
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{
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flash_write(UNLOCK0_ADDR, PROGRAM_CMD);
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flash_write(byte_addr, data);
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uint64_t addr = BASE_ADDR + byte_addr;
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switch (c->bank_width) {
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case 1:
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return qtest_readb(c->qtest, addr);
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case 2:
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return qtest_readw(c->qtest, addr);
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case 4:
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return qtest_readl(c->qtest, addr);
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case 8:
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return qtest_readq(c->qtest, addr);
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default:
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abort();
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}
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}
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/*
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* Convert a flash address expressed in the maximum width of the device as a
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* byte address.
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*/
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static inline uint64_t as_byte_addr(const FlashConfig *c, faddr flash_addr)
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{
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/*
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* Command addresses are always given as addresses in the maximum
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* supported bus size for the flash chip. So an x8/x16 chip in x8 mode
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* uses addresses 0xAAA and 0x555 to unlock because the least significant
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* bit is ignored. (0x555 rather than 0x554 is traditional.)
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*
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* In general we need to multiply by the maximum device width.
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*/
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return flash_addr.addr * c->bank_width;
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}
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/*
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* Return the command value or expected status replicated across all devices.
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*/
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static inline uint64_t replicate(const FlashConfig *c, uint64_t data)
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{
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/* Sanity check our tests. */
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assert((data & ~device_mask(c)) == 0);
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return data;
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}
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static inline void flash_cmd(const FlashConfig *c, faddr cmd_addr,
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uint8_t cmd)
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{
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flash_write(c, as_byte_addr(c, cmd_addr), replicate(c, cmd));
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}
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static inline uint64_t flash_query(const FlashConfig *c, faddr query_addr)
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{
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return flash_read(c, as_byte_addr(c, query_addr));
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}
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static inline uint64_t flash_query_1(const FlashConfig *c, faddr query_addr)
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{
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return flash_query(c, query_addr) & device_mask(c);
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}
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static void unlock(const FlashConfig *c)
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{
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flash_cmd(c, UNLOCK0_ADDR, UNLOCK0_CMD);
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flash_cmd(c, UNLOCK1_ADDR, UNLOCK1_CMD);
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}
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static void reset(const FlashConfig *c)
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{
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flash_cmd(c, FLASH_ADDR(0), RESET_CMD);
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}
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static void sector_erase(const FlashConfig *c, uint64_t byte_addr)
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{
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unlock(c);
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flash_cmd(c, UNLOCK0_ADDR, 0x80);
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unlock(c);
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flash_write(c, byte_addr, replicate(c, SECTOR_ERASE_CMD));
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}
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static void wait_for_completion(const FlashConfig *c, uint64_t byte_addr)
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{
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/* If DQ6 is toggling, step the clock and ensure the toggle stops. */
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const uint64_t dq6 = replicate(c, 0x40);
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if ((flash_read(c, byte_addr) & dq6) ^ (flash_read(c, byte_addr) & dq6)) {
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/* Wait for erase or program to finish. */
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qtest_clock_step_next(c->qtest);
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/* Ensure that DQ6 has stopped toggling. */
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g_assert_cmphex(flash_read(c, byte_addr), ==, flash_read(c, byte_addr));
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}
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}
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static void bypass_program(const FlashConfig *c, uint64_t byte_addr,
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uint16_t data)
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{
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flash_cmd(c, UNLOCK0_ADDR, PROGRAM_CMD);
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flash_write(c, byte_addr, data);
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/*
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* Data isn't valid until DQ6 stops toggling. We don't model this as
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* writes are immediate, but if this changes in the future, we can wait
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* until the program is complete.
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*/
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wait_for_completion(byte_addr);
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wait_for_completion(c, byte_addr);
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}
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static void program(uint64_t byte_addr, uint16_t data)
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static void program(const FlashConfig *c, uint64_t byte_addr, uint16_t data)
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{
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unlock();
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bypass_program(byte_addr, data);
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unlock(c);
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bypass_program(c, byte_addr, data);
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}
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static void chip_erase(void)
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static void chip_erase(const FlashConfig *c)
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{
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unlock();
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flash_write(UNLOCK0_ADDR, 0x80);
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unlock();
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flash_write(UNLOCK0_ADDR, SECTOR_ERASE_CMD);
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unlock(c);
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flash_cmd(c, UNLOCK0_ADDR, 0x80);
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unlock(c);
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flash_cmd(c, UNLOCK0_ADDR, CHIP_ERASE_CMD);
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}
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static void test_flash(void)
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static void test_flash(const void *opaque)
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{
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global_qtest = qtest_initf("-M musicpal,accel=qtest "
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"-drive if=pflash,file=%s,format=raw,copy-on-read",
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image_path);
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const FlashConfig *config = opaque;
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QTestState *qtest;
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qtest = qtest_initf("-M musicpal,accel=qtest"
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" -drive if=pflash,file=%s,format=raw,copy-on-read",
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image_path);
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FlashConfig explicit_config = expand_config_defaults(config);
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explicit_config.qtest = qtest;
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const FlashConfig *c = &explicit_config;
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/* Check the IDs. */
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unlock();
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flash_write(UNLOCK0_ADDR, AUTOSELECT_CMD);
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g_assert_cmphex(flash_read(FLASH_WIDTH * 0x0000), ==, 0x00BF);
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g_assert_cmphex(flash_read(FLASH_WIDTH * 0x0001), ==, 0x236D);
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reset();
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unlock(c);
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flash_cmd(c, UNLOCK0_ADDR, AUTOSELECT_CMD);
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g_assert_cmphex(flash_query(c, FLASH_ADDR(0)), ==, replicate(c, 0xBF));
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if (c->bank_width >= 2) {
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/*
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* XXX: The ID returned by the musicpal flash chip is 16 bits which
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* wouldn't happen with an 8-bit device. It would probably be best to
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* prohibit addresses larger than the device width in pflash_cfi02.c,
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* but then we couldn't test smaller device widths at all.
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*/
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g_assert_cmphex(flash_query(c, FLASH_ADDR(1)), ==,
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replicate(c, 0x236D));
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}
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reset(c);
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/* Check the erase blocks. */
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flash_write(CFI_ADDR, CFI_CMD);
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g_assert_cmphex(flash_read(FLASH_WIDTH * 0x10), ==, 'Q');
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g_assert_cmphex(flash_read(FLASH_WIDTH * 0x11), ==, 'R');
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g_assert_cmphex(flash_read(FLASH_WIDTH * 0x12), ==, 'Y');
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/* Num erase regions. */
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g_assert_cmphex(flash_read(FLASH_WIDTH * 0x2C), >=, 1);
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uint32_t nb_sectors = flash_read(FLASH_WIDTH * 0x2D) +
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(flash_read(FLASH_WIDTH * 0x2E) << 8) + 1;
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uint32_t sector_len = (flash_read(FLASH_WIDTH * 0x2F) << 8) +
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(flash_read(FLASH_WIDTH * 0x30) << 16);
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reset();
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flash_cmd(c, CFI_ADDR, CFI_CMD);
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g_assert_cmphex(flash_query(c, FLASH_ADDR(0x10)), ==, replicate(c, 'Q'));
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g_assert_cmphex(flash_query(c, FLASH_ADDR(0x11)), ==, replicate(c, 'R'));
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g_assert_cmphex(flash_query(c, FLASH_ADDR(0x12)), ==, replicate(c, 'Y'));
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/* Num erase regions. */
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g_assert_cmphex(flash_query_1(c, FLASH_ADDR(0x2C)), >=, 1);
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uint32_t nb_sectors = flash_query_1(c, FLASH_ADDR(0x2D)) +
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(flash_query_1(c, FLASH_ADDR(0x2E)) << 8) + 1;
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uint32_t sector_len = (flash_query_1(c, FLASH_ADDR(0x2F)) << 8) +
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(flash_query_1(c, FLASH_ADDR(0x30)) << 16);
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reset(c);
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const uint64_t dq7 = replicate(c, 0x80);
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const uint64_t dq6 = replicate(c, 0x40);
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/* Erase and program sector. */
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for (uint32_t i = 0; i < nb_sectors; ++i) {
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uint64_t byte_addr = i * sector_len;
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sector_erase(byte_addr);
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sector_erase(c, byte_addr);
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/* Read toggle. */
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uint16_t status0 = flash_read(byte_addr);
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uint64_t status0 = flash_read(c, byte_addr);
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/* DQ7 is 0 during an erase. */
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g_assert_cmphex(status0 & 0x80, ==, 0);
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uint16_t status1 = flash_read(byte_addr);
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g_assert_cmphex(status0 & dq7, ==, 0);
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uint64_t status1 = flash_read(c, byte_addr);
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/* DQ6 toggles during an erase. */
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g_assert_cmphex(status0 & 0x40, !=, status1 & 0x40);
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g_assert_cmphex(status0 & dq6, ==, ~status1 & dq6);
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/* Wait for erase to complete. */
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clock_step_next();
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qtest_clock_step_next(c->qtest);
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/* Ensure DQ6 has stopped toggling. */
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g_assert_cmphex(flash_read(byte_addr), ==, flash_read(byte_addr));
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g_assert_cmphex(flash_read(c, byte_addr), ==, flash_read(c, byte_addr));
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/* Now the data should be valid. */
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g_assert_cmphex(flash_read(byte_addr), ==, 0xFFFF);
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g_assert_cmphex(flash_read(c, byte_addr), ==, bank_mask(c));
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/* Program a bit pattern. */
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program(byte_addr, 0x5555);
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g_assert_cmphex(flash_read(byte_addr), ==, 0x5555);
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program(byte_addr, 0xAA55);
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g_assert_cmphex(flash_read(byte_addr), ==, 0x0055);
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program(c, byte_addr, 0x55);
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g_assert_cmphex(flash_read(c, byte_addr) & 0xFF, ==, 0x55);
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program(c, byte_addr, 0xA5);
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g_assert_cmphex(flash_read(c, byte_addr) & 0xFF, ==, 0x05);
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}
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/* Erase the chip. */
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chip_erase();
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chip_erase(c);
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/* Read toggle. */
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uint16_t status0 = flash_read(0);
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uint64_t status0 = flash_read(c, 0);
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/* DQ7 is 0 during an erase. */
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g_assert_cmphex(status0 & 0x80, ==, 0);
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uint16_t status1 = flash_read(0);
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g_assert_cmphex(status0 & dq7, ==, 0);
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uint64_t status1 = flash_read(c, 0);
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/* DQ6 toggles during an erase. */
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g_assert_cmphex(status0 & 0x40, !=, status1 & 0x40);
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g_assert_cmphex(status0 & dq6, ==, ~status1 & dq6);
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/* Wait for erase to complete. */
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clock_step_next();
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qtest_clock_step_next(c->qtest);
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/* Ensure DQ6 has stopped toggling. */
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g_assert_cmphex(flash_read(0), ==, flash_read(0));
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g_assert_cmphex(flash_read(c, 0), ==, flash_read(c, 0));
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/* Now the data should be valid. */
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g_assert_cmphex(flash_read(0), ==, 0xFFFF);
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for (uint32_t i = 0; i < nb_sectors; ++i) {
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uint64_t byte_addr = i * sector_len;
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g_assert_cmphex(flash_read(c, byte_addr), ==, bank_mask(c));
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}
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/* Unlock bypass */
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unlock();
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flash_write(UNLOCK0_ADDR, UNLOCK_BYPASS_CMD);
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bypass_program(0, 0x0123);
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bypass_program(2, 0x4567);
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bypass_program(4, 0x89AB);
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unlock(c);
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flash_cmd(c, UNLOCK0_ADDR, UNLOCK_BYPASS_CMD);
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bypass_program(c, 0 * c->bank_width, 0x01);
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bypass_program(c, 1 * c->bank_width, 0x23);
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bypass_program(c, 2 * c->bank_width, 0x45);
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/*
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* Test that bypass programming, unlike normal programming can use any
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* address for the PROGRAM_CMD.
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*/
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flash_write(6, PROGRAM_CMD);
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flash_write(6, 0xCDEF);
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wait_for_completion(6);
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flash_write(0, UNLOCK_BYPASS_RESET_CMD);
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bypass_program(8, 0x55AA); /* Should fail. */
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g_assert_cmphex(flash_read(0), ==, 0x0123);
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g_assert_cmphex(flash_read(2), ==, 0x4567);
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g_assert_cmphex(flash_read(4), ==, 0x89AB);
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g_assert_cmphex(flash_read(6), ==, 0xCDEF);
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g_assert_cmphex(flash_read(8), ==, 0xFFFF);
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flash_cmd(c, FLASH_ADDR(3 * c->bank_width), PROGRAM_CMD);
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flash_write(c, 3 * c->bank_width, 0x67);
|
||||
wait_for_completion(c, 3 * c->bank_width);
|
||||
flash_cmd(c, FLASH_ADDR(0), UNLOCK_BYPASS_RESET_CMD);
|
||||
bypass_program(c, 4 * c->bank_width, 0x89); /* Should fail. */
|
||||
g_assert_cmphex(flash_read(c, 0 * c->bank_width), ==, 0x01);
|
||||
g_assert_cmphex(flash_read(c, 1 * c->bank_width), ==, 0x23);
|
||||
g_assert_cmphex(flash_read(c, 2 * c->bank_width), ==, 0x45);
|
||||
g_assert_cmphex(flash_read(c, 3 * c->bank_width), ==, 0x67);
|
||||
g_assert_cmphex(flash_read(c, 4 * c->bank_width), ==, bank_mask(c));
|
||||
|
||||
/* Test ignored high order bits of address. */
|
||||
flash_write(FLASH_WIDTH * 0x5555, UNLOCK0_CMD);
|
||||
flash_write(FLASH_WIDTH * 0x2AAA, UNLOCK1_CMD);
|
||||
flash_write(FLASH_WIDTH * 0x5555, AUTOSELECT_CMD);
|
||||
g_assert_cmpint(flash_read(FLASH_WIDTH * 0x0000), ==, 0x00BF);
|
||||
g_assert_cmpint(flash_read(FLASH_WIDTH * 0x0001), ==, 0x236D);
|
||||
reset();
|
||||
flash_cmd(c, FLASH_ADDR(0x5555), UNLOCK0_CMD);
|
||||
flash_cmd(c, FLASH_ADDR(0x2AAA), UNLOCK1_CMD);
|
||||
flash_cmd(c, FLASH_ADDR(0x5555), AUTOSELECT_CMD);
|
||||
g_assert_cmphex(flash_query(c, FLASH_ADDR(0)), ==, replicate(c, 0xBF));
|
||||
reset(c);
|
||||
|
||||
qtest_quit(global_qtest);
|
||||
qtest_quit(qtest);
|
||||
}
|
||||
|
||||
static void cleanup(void *opaque)
|
||||
@ -206,6 +355,17 @@ static void cleanup(void *opaque)
|
||||
unlink(image_path);
|
||||
}
|
||||
|
||||
/*
|
||||
* XXX: Tests are limited to bank_width = 2 for now because that's what
|
||||
* hw/arm/musicpal.c has.
|
||||
*/
|
||||
static const FlashConfig configuration[] = {
|
||||
/* One x16 device. */
|
||||
{
|
||||
.bank_width = 2,
|
||||
},
|
||||
};
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
int fd = mkstemp(image_path);
|
||||
@ -214,19 +374,27 @@ int main(int argc, char **argv)
|
||||
strerror(errno));
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
if (ftruncate(fd, 8 * 1024 * 1024) < 0) {
|
||||
if (ftruncate(fd, FLASH_SIZE) < 0) {
|
||||
int error_code = errno;
|
||||
close(fd);
|
||||
unlink(image_path);
|
||||
g_printerr("Failed to truncate file %s to 8 MB: %s\n", image_path,
|
||||
strerror(error_code));
|
||||
g_printerr("Failed to truncate file %s to %u MB: %s\n", image_path,
|
||||
FLASH_SIZE, strerror(error_code));
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
close(fd);
|
||||
|
||||
qtest_add_abrt_handler(cleanup, NULL);
|
||||
g_test_init(&argc, &argv, NULL);
|
||||
qtest_add_func("pflash-cfi02", test_flash);
|
||||
|
||||
size_t nb_configurations = sizeof configuration / sizeof configuration[0];
|
||||
for (size_t i = 0; i < nb_configurations; ++i) {
|
||||
const FlashConfig *config = &configuration[i];
|
||||
char *path = g_strdup_printf("pflash-cfi02/%d",
|
||||
config->bank_width);
|
||||
qtest_add_data_func(path, config, test_flash);
|
||||
g_free(path);
|
||||
}
|
||||
int result = g_test_run();
|
||||
cleanup(NULL);
|
||||
return result;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user