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initial sparc32 lance and pcnet merge

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2142 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard 2006-09-03 16:07:02 +00:00
parent c03b0f0fd8
commit 91cc029598
2 changed files with 330 additions and 591 deletions
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474
hw/lance.c
View File

@ -1,474 +0,0 @@
/*
* QEMU Lance emulation
*
* Copyright (c) 2003-2005 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "vl.h"
/* debug LANCE card */
//#define DEBUG_LANCE
#ifdef DEBUG_LANCE
#define DPRINTF(fmt, args...) \
do { printf("LANCE: " fmt , ##args); } while (0)
#else
#define DPRINTF(fmt, args...)
#endif
#ifndef LANCE_LOG_TX_BUFFERS
#define LANCE_LOG_TX_BUFFERS 4
#define LANCE_LOG_RX_BUFFERS 4
#endif
#define LE_CSR0 0
#define LE_CSR1 1
#define LE_CSR2 2
#define LE_CSR3 3
#define LE_NREGS (LE_CSR3 + 1)
#define LE_MAXREG LE_CSR3
#define LE_RDP 0
#define LE_RAP 1
#define LE_MO_PROM 0x8000 /* Enable promiscuous mode */
#define LE_C0_ERR 0x8000 /* Error: set if BAB, SQE, MISS or ME is set */
#define LE_C0_BABL 0x4000 /* BAB: Babble: tx timeout. */
#define LE_C0_CERR 0x2000 /* SQE: Signal quality error */
#define LE_C0_MISS 0x1000 /* MISS: Missed a packet */
#define LE_C0_MERR 0x0800 /* ME: Memory error */
#define LE_C0_RINT 0x0400 /* Received interrupt */
#define LE_C0_TINT 0x0200 /* Transmitter Interrupt */
#define LE_C0_IDON 0x0100 /* IFIN: Init finished. */
#define LE_C0_INTR 0x0080 /* Interrupt or error */
#define LE_C0_INEA 0x0040 /* Interrupt enable */
#define LE_C0_RXON 0x0020 /* Receiver on */
#define LE_C0_TXON 0x0010 /* Transmitter on */
#define LE_C0_TDMD 0x0008 /* Transmitter demand */
#define LE_C0_STOP 0x0004 /* Stop the card */
#define LE_C0_STRT 0x0002 /* Start the card */
#define LE_C0_INIT 0x0001 /* Init the card */
#define LE_C3_BSWP 0x4 /* SWAP */
#define LE_C3_ACON 0x2 /* ALE Control */
#define LE_C3_BCON 0x1 /* Byte control */
/* Receive message descriptor 1 */
#define LE_R1_OWN 0x80 /* Who owns the entry */
#define LE_R1_ERR 0x40 /* Error: if FRA, OFL, CRC or BUF is set */
#define LE_R1_FRA 0x20 /* FRA: Frame error */
#define LE_R1_OFL 0x10 /* OFL: Frame overflow */
#define LE_R1_CRC 0x08 /* CRC error */
#define LE_R1_BUF 0x04 /* BUF: Buffer error */
#define LE_R1_SOP 0x02 /* Start of packet */
#define LE_R1_EOP 0x01 /* End of packet */
#define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */
#define LE_T1_OWN 0x80 /* Lance owns the packet */
#define LE_T1_ERR 0x40 /* Error summary */
#define LE_T1_EMORE 0x10 /* Error: more than one retry needed */
#define LE_T1_EONE 0x08 /* Error: one retry needed */
#define LE_T1_EDEF 0x04 /* Error: deferred */
#define LE_T1_SOP 0x02 /* Start of packet */
#define LE_T1_EOP 0x01 /* End of packet */
#define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */
#define LE_T3_BUF 0x8000 /* Buffer error */
#define LE_T3_UFL 0x4000 /* Error underflow */
#define LE_T3_LCOL 0x1000 /* Error late collision */
#define LE_T3_CLOS 0x0800 /* Error carrier loss */
#define LE_T3_RTY 0x0400 /* Error retry */
#define LE_T3_TDR 0x03ff /* Time Domain Reflectometry counter */
#define TX_RING_SIZE (1 << (LANCE_LOG_TX_BUFFERS))
#define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
#define TX_RING_LEN_BITS ((LANCE_LOG_TX_BUFFERS) << 29)
#define RX_RING_SIZE (1 << (LANCE_LOG_RX_BUFFERS))
#define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
#define RX_RING_LEN_BITS ((LANCE_LOG_RX_BUFFERS) << 29)
#define PKT_BUF_SZ 1544
#define RX_BUFF_SIZE PKT_BUF_SZ
#define TX_BUFF_SIZE PKT_BUF_SZ
struct lance_rx_desc {
unsigned short rmd0; /* low address of packet */
unsigned char rmd1_bits; /* descriptor bits */
unsigned char rmd1_hadr; /* high address of packet */
short length; /* This length is 2s complement (negative)!
* Buffer length
*/
unsigned short mblength; /* This is the actual number of bytes received */
};
struct lance_tx_desc {
unsigned short tmd0; /* low address of packet */
unsigned char tmd1_bits; /* descriptor bits */
unsigned char tmd1_hadr; /* high address of packet */
short length; /* Length is 2s complement (negative)! */
unsigned short misc;
};
/* The LANCE initialization block, described in databook. */
/* On the Sparc, this block should be on a DMA region */
struct lance_init_block {
unsigned short mode; /* Pre-set mode (reg. 15) */
unsigned char phys_addr[6]; /* Physical ethernet address */
unsigned filter[2]; /* Multicast filter. */
/* Receive and transmit ring base, along with extra bits. */
unsigned short rx_ptr; /* receive descriptor addr */
unsigned short rx_len; /* receive len and high addr */
unsigned short tx_ptr; /* transmit descriptor addr */
unsigned short tx_len; /* transmit len and high addr */
/* The Tx and Rx ring entries must aligned on 8-byte boundaries. */
struct lance_rx_desc brx_ring[RX_RING_SIZE];
struct lance_tx_desc btx_ring[TX_RING_SIZE];
char tx_buf[TX_RING_SIZE][TX_BUFF_SIZE];
char pad[2]; /* align rx_buf for copy_and_sum(). */
char rx_buf[RX_RING_SIZE][RX_BUFF_SIZE];
};
#define LEDMA_REGS 4
#define LEDMA_MAXADDR (LEDMA_REGS * 4 - 1)
typedef struct LANCEState {
VLANClientState *vc;
uint8_t macaddr[6]; /* init mac address */
uint32_t leptr;
uint16_t addr;
uint16_t regs[LE_NREGS];
uint8_t phys[6]; /* mac address */
int irq;
unsigned int rxptr, txptr;
uint32_t ledmaregs[LEDMA_REGS];
} LANCEState;
static void lance_send(void *opaque);
static void lance_reset(void *opaque)
{
LANCEState *s = opaque;
memcpy(s->phys, s->macaddr, 6);
s->rxptr = 0;
s->txptr = 0;
memset(s->regs, 0, LE_NREGS * 2);
s->regs[LE_CSR0] = LE_C0_STOP;
memset(s->ledmaregs, 0, LEDMA_REGS * 4);
}
static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)
{
LANCEState *s = opaque;
uint32_t saddr;
saddr = addr & LE_MAXREG;
switch (saddr >> 1) {
case LE_RDP:
DPRINTF("read dreg[%d] = %4.4x\n", s->addr, s->regs[s->addr]);
return s->regs[s->addr];
case LE_RAP:
DPRINTF("read areg = %4.4x\n", s->addr);
return s->addr;
default:
DPRINTF("read unknown(%d)\n", saddr >> 1);
break;
}
return 0;
}
static void lance_mem_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
LANCEState *s = opaque;
uint32_t saddr;
uint16_t reg;
saddr = addr & LE_MAXREG;
switch (saddr >> 1) {
case LE_RDP:
DPRINTF("write dreg[%d] = %4.4x\n", s->addr, val);
switch (s->addr) {
case LE_CSR0:
if (val & LE_C0_STOP) {
s->regs[LE_CSR0] = LE_C0_STOP;
break;
}
reg = s->regs[LE_CSR0];
// 1 = clear for some bits
reg &= ~(val & 0x7f00);
// generated bits
reg &= ~(LE_C0_ERR | LE_C0_INTR);
if (reg & 0x7100)
reg |= LE_C0_ERR;
if (reg & 0x7f00)
reg |= LE_C0_INTR;
// direct bit
reg &= ~LE_C0_INEA;
reg |= val & LE_C0_INEA;
// exclusive bits
if (val & LE_C0_INIT) {
reg |= LE_C0_IDON | LE_C0_INIT;
reg &= ~LE_C0_STOP;
} else if (val & LE_C0_STRT) {
reg |= LE_C0_STRT | LE_C0_RXON | LE_C0_TXON;
reg &= ~LE_C0_STOP;
}
s->regs[LE_CSR0] = reg;
break;
case LE_CSR1:
s->leptr = (s->leptr & 0xffff0000) | (val & 0xffff);
s->regs[s->addr] = val;
break;
case LE_CSR2:
s->leptr = (s->leptr & 0xffff) | ((val & 0xffff) << 16);
s->regs[s->addr] = val;
break;
case LE_CSR3:
s->regs[s->addr] = val;
break;
}
break;
case LE_RAP:
DPRINTF("write areg = %4.4x\n", val);
if (val < LE_NREGS)
s->addr = val;
break;
default:
DPRINTF("write unknown(%d) = %4.4x\n", saddr >> 1, val);
break;
}
lance_send(s);
}
static CPUReadMemoryFunc *lance_mem_read[3] = {
lance_mem_readw,
lance_mem_readw,
lance_mem_readw,
};
static CPUWriteMemoryFunc *lance_mem_write[3] = {
lance_mem_writew,
lance_mem_writew,
lance_mem_writew,
};
#define MIN_BUF_SIZE 60
static int lance_can_receive(void *opaque)
{
return 1;
}
static void lance_receive(void *opaque, const uint8_t * buf, int size)
{
LANCEState *s = opaque;
uint32_t dmaptr = s->leptr + s->ledmaregs[3];
struct lance_init_block *ib;
unsigned int i, old_rxptr;
uint16_t temp16;
uint8_t temp8;
DPRINTF("receive size %d\n", size);
if ((s->regs[LE_CSR0] & LE_C0_STOP) == LE_C0_STOP)
return;
ib = (void *) iommu_translate(dmaptr);
old_rxptr = s->rxptr;
for (i = s->rxptr; i != ((old_rxptr - 1) & RX_RING_MOD_MASK);
i = (i + 1) & RX_RING_MOD_MASK) {
cpu_physical_memory_read((uint32_t) & ib->brx_ring[i].rmd1_bits,
(void *) &temp8, 1);
if (temp8 == (LE_R1_OWN)) {
s->rxptr = (s->rxptr + 1) & RX_RING_MOD_MASK;
temp16 = size + 4;
bswap16s(&temp16);
cpu_physical_memory_write((uint32_t) & ib->brx_ring[i].
mblength, (void *) &temp16, 2);
cpu_physical_memory_write((uint32_t) & ib->rx_buf[i], buf,
size);
temp8 = LE_R1_POK;
cpu_physical_memory_write((uint32_t) & ib->brx_ring[i].
rmd1_bits, (void *) &temp8, 1);
s->regs[LE_CSR0] |= LE_C0_RINT | LE_C0_INTR;
if (s->regs[LE_CSR0] & LE_C0_INEA)
pic_set_irq(s->irq, 1);
DPRINTF("got packet, len %d\n", size);
return;
}
}
}
static void lance_send(void *opaque)
{
LANCEState *s = opaque;
uint32_t dmaptr = s->leptr + s->ledmaregs[3];
struct lance_init_block *ib;
unsigned int i, old_txptr;
uint16_t temp16;
uint8_t temp8;
char pkt_buf[PKT_BUF_SZ];
DPRINTF("sending packet? (csr0 %4.4x)\n", s->regs[LE_CSR0]);
if ((s->regs[LE_CSR0] & LE_C0_STOP) == LE_C0_STOP)
return;
ib = (void *) iommu_translate(dmaptr);
DPRINTF("sending packet? (dmaptr %8.8x) (ib %p) (btx_ring %p)\n",
dmaptr, ib, &ib->btx_ring);
old_txptr = s->txptr;
for (i = s->txptr; i != ((old_txptr - 1) & TX_RING_MOD_MASK);
i = (i + 1) & TX_RING_MOD_MASK) {
cpu_physical_memory_read((uint32_t) & ib->btx_ring[i].tmd1_bits,
(void *) &temp8, 1);
if (temp8 == (LE_T1_POK | LE_T1_OWN)) {
cpu_physical_memory_read((uint32_t) & ib->btx_ring[i].length,
(void *) &temp16, 2);
bswap16s(&temp16);
temp16 = (~temp16) + 1;
cpu_physical_memory_read((uint32_t) & ib->tx_buf[i], pkt_buf,
temp16);
DPRINTF("sending packet, len %d\n", temp16);
qemu_send_packet(s->vc, pkt_buf, temp16);
temp8 = LE_T1_POK;
cpu_physical_memory_write((uint32_t) & ib->btx_ring[i].
tmd1_bits, (void *) &temp8, 1);
s->txptr = (s->txptr + 1) & TX_RING_MOD_MASK;
s->regs[LE_CSR0] |= LE_C0_TINT | LE_C0_INTR;
}
}
if ((s->regs[LE_CSR0] & LE_C0_INTR) && (s->regs[LE_CSR0] & LE_C0_INEA))
pic_set_irq(s->irq, 1);
}
static uint32_t ledma_mem_readl(void *opaque, target_phys_addr_t addr)
{
LANCEState *s = opaque;
uint32_t saddr;
saddr = (addr & LEDMA_MAXADDR) >> 2;
return s->ledmaregs[saddr];
}
static void ledma_mem_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
LANCEState *s = opaque;
uint32_t saddr;
saddr = (addr & LEDMA_MAXADDR) >> 2;
s->ledmaregs[saddr] = val;
}
static CPUReadMemoryFunc *ledma_mem_read[3] = {
ledma_mem_readl,
ledma_mem_readl,
ledma_mem_readl,
};
static CPUWriteMemoryFunc *ledma_mem_write[3] = {
ledma_mem_writel,
ledma_mem_writel,
ledma_mem_writel,
};
static void lance_save(QEMUFile * f, void *opaque)
{
LANCEState *s = opaque;
int i;
qemu_put_be32s(f, &s->leptr);
qemu_put_be16s(f, &s->addr);
for (i = 0; i < LE_NREGS; i++)
qemu_put_be16s(f, &s->regs[i]);
qemu_put_buffer(f, s->phys, 6);
qemu_put_be32s(f, &s->irq);
for (i = 0; i < LEDMA_REGS; i++)
qemu_put_be32s(f, &s->ledmaregs[i]);
}
static int lance_load(QEMUFile * f, void *opaque, int version_id)
{
LANCEState *s = opaque;
int i;
if (version_id != 1)
return -EINVAL;
qemu_get_be32s(f, &s->leptr);
qemu_get_be16s(f, &s->addr);
for (i = 0; i < LE_NREGS; i++)
qemu_get_be16s(f, &s->regs[i]);
qemu_get_buffer(f, s->phys, 6);
qemu_get_be32s(f, &s->irq);
for (i = 0; i < LEDMA_REGS; i++)
qemu_get_be32s(f, &s->ledmaregs[i]);
return 0;
}
void lance_init(NICInfo * nd, int irq, uint32_t leaddr, uint32_t ledaddr)
{
LANCEState *s;
int lance_io_memory, ledma_io_memory;
s = qemu_mallocz(sizeof(LANCEState));
if (!s)
return;
s->irq = irq;
lance_io_memory =
cpu_register_io_memory(0, lance_mem_read, lance_mem_write, s);
cpu_register_physical_memory(leaddr, 4, lance_io_memory);
ledma_io_memory =
cpu_register_io_memory(0, ledma_mem_read, ledma_mem_write, s);
cpu_register_physical_memory(ledaddr, 16, ledma_io_memory);
memcpy(s->macaddr, nd->macaddr, 6);
lance_reset(s);
s->vc =
qemu_new_vlan_client(nd->vlan, lance_receive, lance_can_receive,
s);
snprintf(s->vc->info_str, sizeof(s->vc->info_str),
"lance macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
s->macaddr[0],
s->macaddr[1],
s->macaddr[2], s->macaddr[3], s->macaddr[4], s->macaddr[5]);
register_savevm("lance", leaddr, 1, lance_save, lance_load, s);
qemu_register_reset(lance_reset, s);
}

447
hw/pcnet.c
View File

@ -27,6 +27,16 @@
* AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
*/
/*
* On Sparc32, this is the Lance (Am7990) part of chip STP2000 (Master I/O), also
* produced as NCR89C100. See
* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
* and
* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt
*/
/* TODO: remove little endian host assumptions */
#include "vl.h"
//#define PCNET_DEBUG
@ -46,11 +56,12 @@ typedef struct PCNetState_st PCNetState;
struct PCNetState_st {
PCIDevice dev;
PCIDevice *pci_dev;
VLANClientState *vc;
NICInfo *nd;
QEMUTimer *poll_timer;
int mmio_io_addr, rap, isr, lnkst;
target_phys_addr_t rdra, tdra;
int mmio_index, rap, isr, lnkst;
uint32_t rdra, tdra;
uint8_t prom[16];
uint16_t csr[128];
uint16_t bcr[32];
@ -58,6 +69,12 @@ struct PCNetState_st {
int xmit_pos, recv_pos;
uint8_t buffer[4096];
int tx_busy;
void (*set_irq_cb)(void *s, int isr);
void (*phys_mem_read)(void *dma_opaque, target_phys_addr_t addr,
uint8_t *buf, int len);
void (*phys_mem_write)(void *dma_opaque, target_phys_addr_t addr,
uint8_t *buf, int len);
void *dma_opaque;
};
/* XXX: using bitfields for target memory structures is almost surely
@ -99,6 +116,7 @@ struct qemu_ether_header {
#define CSR_TXON(S) !!(((S)->csr[0])&0x0010)
#define CSR_RXON(S) !!(((S)->csr[0])&0x0020)
#define CSR_INEA(S) !!(((S)->csr[0])&0x0040)
#define CSR_BIGENDIAN(S) !!(((S)->csr[3])&0x0004)
#define CSR_LAPPEN(S) !!(((S)->csr[3])&0x0020)
#define CSR_DXSUFLO(S) !!(((S)->csr[3])&0x0040)
#define CSR_ASTRP_RCV(S) !!(((S)->csr[4])&0x0800)
@ -147,35 +165,19 @@ struct qemu_ether_header {
struct pcnet_initblk16 {
uint16_t mode;
uint16_t padr1;
uint16_t padr2;
uint16_t padr3;
uint16_t ladrf1;
uint16_t ladrf2;
uint16_t ladrf3;
uint16_t ladrf4;
unsigned PACKED_FIELD(rdra:24);
unsigned PACKED_FIELD(res1:5);
unsigned PACKED_FIELD(rlen:3);
unsigned PACKED_FIELD(tdra:24);
unsigned PACKED_FIELD(res2:5);
unsigned PACKED_FIELD(tlen:3);
uint16_t padr[3];
uint16_t ladrf[4];
uint32_t rdra;
uint32_t tdra;
};
struct pcnet_initblk32 {
uint16_t mode;
unsigned PACKED_FIELD(res1:4);
unsigned PACKED_FIELD(rlen:4);
unsigned PACKED_FIELD(res2:4);
unsigned PACKED_FIELD(tlen:4);
uint16_t padr1;
uint16_t padr2;
uint16_t padr3;
uint8_t rlen;
uint8_t tlen;
uint16_t padr[3];
uint16_t _res;
uint16_t ladrf1;
uint16_t ladrf2;
uint16_t ladrf3;
uint16_t ladrf4;
uint16_t ladrf[4];
uint32_t rdra;
uint32_t tdra;
};
@ -255,22 +257,32 @@ static inline void pcnet_tmd_load(PCNetState *s, struct pcnet_TMD *tmd, target_p
{
if (!BCR_SWSTYLE(s)) {
uint16_t xda[4];
cpu_physical_memory_read(addr,
s->phys_mem_read(s->dma_opaque, addr,
(void *)&xda[0], sizeof(xda));
((uint32_t *)tmd)[0] = (xda[0]&0xffff) |
if (CSR_BIGENDIAN(s)) {
((uint32_t *)tmd)[0] = be16_to_cpu(xda[0]) |
((be16_to_cpu(xda[1]) & 0x00ff) << 16);
((uint32_t *)tmd)[1] = be16_to_cpu(xda[2]) |
((be16_to_cpu(xda[1]) & 0xff00) << 16);
((uint32_t *)tmd)[2] =
(be16_to_cpu(xda[3]) & 0xffff) << 16;
((uint32_t *)tmd)[3] = 0;
} else {
((uint32_t *)tmd)[0] = (xda[0]&0xffff) |
((xda[1]&0x00ff) << 16);
((uint32_t *)tmd)[1] = (xda[2]&0xffff)|
((uint32_t *)tmd)[1] = (xda[2]&0xffff)|
((xda[1] & 0xff00) << 16);
((uint32_t *)tmd)[2] =
((uint32_t *)tmd)[2] =
(xda[3] & 0xffff) << 16;
((uint32_t *)tmd)[3] = 0;
((uint32_t *)tmd)[3] = 0;
}
}
else
if (BCR_SWSTYLE(s) != 3)
cpu_physical_memory_read(addr, (void *)tmd, 16);
s->phys_mem_read(s->dma_opaque, addr, (void *)tmd, 16);
else {
uint32_t xda[4];
cpu_physical_memory_read(addr,
s->phys_mem_read(s->dma_opaque, addr,
(void *)&xda[0], sizeof(xda));
((uint32_t *)tmd)[0] = xda[2];
((uint32_t *)tmd)[1] = xda[1];
@ -283,24 +295,32 @@ static inline void pcnet_tmd_store(PCNetState *s, struct pcnet_TMD *tmd, target_
{
if (!BCR_SWSTYLE(s)) {
uint16_t xda[4];
xda[0] = ((uint32_t *)tmd)[0] & 0xffff;
xda[1] = ((((uint32_t *)tmd)[0]>>16)&0x00ff) |
((((uint32_t *)tmd)[1]>>16)&0xff00);
xda[2] = ((uint32_t *)tmd)[1] & 0xffff;
xda[3] = ((uint32_t *)tmd)[2] >> 16;
cpu_physical_memory_write(addr,
if (CSR_BIGENDIAN(s)) {
xda[0] = cpu_to_be16(((uint32_t *)tmd)[0] & 0xffff);
xda[1] = cpu_to_be16(((((uint32_t *)tmd)[0] >> 16) & 0x00ff) |
((((uint32_t *)tmd)[1] >> 16) & 0xff00));
xda[2] = cpu_to_be16(((uint32_t *)tmd)[1] & 0xffff);
xda[3] = cpu_to_be16(((uint32_t *)tmd)[2] >> 16);
} else {
xda[0] = ((uint32_t *)tmd)[0] & 0xffff;
xda[1] = ((((uint32_t *)tmd)[0]>>16)&0x00ff) |
((((uint32_t *)tmd)[1]>>16)&0xff00);
xda[2] = ((uint32_t *)tmd)[1] & 0xffff;
xda[3] = ((uint32_t *)tmd)[2] >> 16;
}
s->phys_mem_write(s->dma_opaque, addr,
(void *)&xda[0], sizeof(xda));
}
else {
if (BCR_SWSTYLE(s) != 3)
cpu_physical_memory_write(addr, (void *)tmd, 16);
s->phys_mem_write(s->dma_opaque, addr, (void *)tmd, 16);
else {
uint32_t xda[4];
xda[0] = ((uint32_t *)tmd)[2];
xda[1] = ((uint32_t *)tmd)[1];
xda[2] = ((uint32_t *)tmd)[0];
xda[3] = ((uint32_t *)tmd)[3];
cpu_physical_memory_write(addr,
s->phys_mem_write(s->dma_opaque, addr,
(void *)&xda[0], sizeof(xda));
}
}
@ -310,21 +330,30 @@ static inline void pcnet_rmd_load(PCNetState *s, struct pcnet_RMD *rmd, target_p
{
if (!BCR_SWSTYLE(s)) {
uint16_t rda[4];
cpu_physical_memory_read(addr,
s->phys_mem_read(s->dma_opaque, addr,
(void *)&rda[0], sizeof(rda));
((uint32_t *)rmd)[0] = (rda[0]&0xffff)|
if (CSR_BIGENDIAN(s)) {
((uint32_t *)rmd)[0] = (be16_to_cpu(rda[0]) & 0xffff) |
((be16_to_cpu(rda[1]) & 0x00ff) << 16);
((uint32_t *)rmd)[1] = (be16_to_cpu(rda[2]) & 0xffff) |
((be16_to_cpu(rda[1]) & 0xff00) << 16);
((uint32_t *)rmd)[2] = be16_to_cpu(rda[3]) & 0xffff;
((uint32_t *)rmd)[3] = 0;
} else {
((uint32_t *)rmd)[0] = (rda[0]&0xffff)|
((rda[1] & 0x00ff) << 16);
((uint32_t *)rmd)[1] = (rda[2]&0xffff)|
((uint32_t *)rmd)[1] = (rda[2]&0xffff)|
((rda[1] & 0xff00) << 16);
((uint32_t *)rmd)[2] = rda[3] & 0xffff;
((uint32_t *)rmd)[3] = 0;
((uint32_t *)rmd)[2] = rda[3] & 0xffff;
((uint32_t *)rmd)[3] = 0;
}
}
else
if (BCR_SWSTYLE(s) != 3)
cpu_physical_memory_read(addr, (void *)rmd, 16);
s->phys_mem_read(s->dma_opaque, addr, (void *)rmd, 16);
else {
uint32_t rda[4];
cpu_physical_memory_read(addr,
s->phys_mem_read(s->dma_opaque, addr,
(void *)&rda[0], sizeof(rda));
((uint32_t *)rmd)[0] = rda[2];
((uint32_t *)rmd)[1] = rda[1];
@ -336,25 +365,33 @@ static inline void pcnet_rmd_load(PCNetState *s, struct pcnet_RMD *rmd, target_p
static inline void pcnet_rmd_store(PCNetState *s, struct pcnet_RMD *rmd, target_phys_addr_t addr)
{
if (!BCR_SWSTYLE(s)) {
uint16_t rda[4]; \
rda[0] = ((uint32_t *)rmd)[0] & 0xffff; \
rda[1] = ((((uint32_t *)rmd)[0]>>16)&0xff)|\
((((uint32_t *)rmd)[1]>>16)&0xff00);\
rda[2] = ((uint32_t *)rmd)[1] & 0xffff; \
rda[3] = ((uint32_t *)rmd)[2] & 0xffff; \
cpu_physical_memory_write(addr, \
(void *)&rda[0], sizeof(rda)); \
uint16_t rda[4];
if (CSR_BIGENDIAN(s)) {
rda[0] = cpu_to_be16(((uint32_t *)rmd)[0] & 0xffff);
rda[1] = cpu_to_be16(((((uint32_t *)rmd)[0] >> 16) & 0xff) |
((((uint32_t *)rmd)[1] >> 16) & 0xff00));
rda[2] = cpu_to_be16(((uint32_t *)rmd)[1] & 0xffff);
rda[3] = cpu_to_be16(((uint32_t *)rmd)[2] & 0xffff);
} else {
rda[0] = ((uint32_t *)rmd)[0] & 0xffff;
rda[1] = ((((uint32_t *)rmd)[0]>>16)&0xff)|
((((uint32_t *)rmd)[1]>>16)&0xff00);
rda[2] = ((uint32_t *)rmd)[1] & 0xffff;
rda[3] = ((uint32_t *)rmd)[2] & 0xffff;
}
s->phys_mem_write(s->dma_opaque, addr,
(void *)&rda[0], sizeof(rda));
}
else {
if (BCR_SWSTYLE(s) != 3)
cpu_physical_memory_write(addr, (void *)rmd, 16);
s->phys_mem_write(s->dma_opaque, addr, (void *)rmd, 16);
else {
uint32_t rda[4];
rda[0] = ((uint32_t *)rmd)[2];
rda[1] = ((uint32_t *)rmd)[1];
rda[2] = ((uint32_t *)rmd)[0];
rda[3] = ((uint32_t *)rmd)[3];
cpu_physical_memory_write(addr,
s->phys_mem_write(s->dma_opaque, addr,
(void *)&rda[0], sizeof(rda));
}
}
@ -391,7 +428,7 @@ static inline void pcnet_rmd_store(PCNetState *s, struct pcnet_RMD *rmd, target_
case 0x00: \
do { \
uint16_t rda[4]; \
cpu_physical_memory_read((ADDR), \
s->phys_mem_read(s->dma_opaque, (ADDR), \
(void *)&rda[0], sizeof(rda)); \
(RES) |= (rda[2] & 0xf000)!=0xf000; \
(RES) |= (rda[3] & 0xf000)!=0x0000; \
@ -401,7 +438,7 @@ static inline void pcnet_rmd_store(PCNetState *s, struct pcnet_RMD *rmd, target_
case 0x02: \
do { \
uint32_t rda[4]; \
cpu_physical_memory_read((ADDR), \
s->phys_mem_read(s->dma_opaque, (ADDR), \
(void *)&rda[0], sizeof(rda)); \
(RES) |= (rda[1] & 0x0000f000L)!=0x0000f000L; \
(RES) |= (rda[2] & 0x0000f000L)!=0x00000000L; \
@ -410,7 +447,7 @@ static inline void pcnet_rmd_store(PCNetState *s, struct pcnet_RMD *rmd, target_
case 0x03: \
do { \
uint32_t rda[4]; \
cpu_physical_memory_read((ADDR), \
s->phys_mem_read(s->dma_opaque, (ADDR), \
(void *)&rda[0], sizeof(rda)); \
(RES) |= (rda[0] & 0x0000f000L)!=0x00000000L; \
(RES) |= (rda[1] & 0x0000f000L)!=0x0000f000L; \
@ -424,7 +461,7 @@ static inline void pcnet_rmd_store(PCNetState *s, struct pcnet_RMD *rmd, target_
case 0x00: \
do { \
uint16_t xda[4]; \
cpu_physical_memory_read((ADDR), \
s->phys_mem_read(s->dma_opaque, (ADDR), \
(void *)&xda[0], sizeof(xda)); \
(RES) |= (xda[2] & 0xf000)!=0xf000;\
} while (0); \
@ -434,7 +471,7 @@ static inline void pcnet_rmd_store(PCNetState *s, struct pcnet_RMD *rmd, target_
case 0x03: \
do { \
uint32_t xda[4]; \
cpu_physical_memory_read((ADDR), \
s->phys_mem_read(s->dma_opaque, (ADDR), \
(void *)&xda[0], sizeof(xda)); \
(RES) |= (xda[1] & 0x0000f000L)!=0x0000f000L; \
} while (0); \
@ -721,51 +758,86 @@ static void pcnet_update_irq(PCNetState *s)
printf("pcnet: INTA=%d\n", isr);
#endif
}
pci_set_irq(&s->dev, 0, isr);
s->isr = isr;
s->set_irq_cb(s, isr);
s->isr = isr;
}
static void pcnet_init(PCNetState *s)
{
int rlen, tlen;
uint16_t *padr, *ladrf, mode;
uint32_t rdra, tdra;
#ifdef PCNET_DEBUG
printf("pcnet_init init_addr=0x%08x\n", PHYSADDR(s,CSR_IADR(s)));
#endif
#define PCNET_INIT() do { \
cpu_physical_memory_read(PHYSADDR(s,CSR_IADR(s)), \
(uint8_t *)&initblk, sizeof(initblk)); \
s->csr[15] = le16_to_cpu(initblk.mode); \
CSR_RCVRL(s) = (initblk.rlen < 9) ? (1 << initblk.rlen) : 512; \
CSR_XMTRL(s) = (initblk.tlen < 9) ? (1 << initblk.tlen) : 512; \
s->csr[ 6] = (initblk.tlen << 12) | (initblk.rlen << 8); \
s->csr[ 8] = le16_to_cpu(initblk.ladrf1); \
s->csr[ 9] = le16_to_cpu(initblk.ladrf2); \
s->csr[10] = le16_to_cpu(initblk.ladrf3); \
s->csr[11] = le16_to_cpu(initblk.ladrf4); \
s->csr[12] = le16_to_cpu(initblk.padr1); \
s->csr[13] = le16_to_cpu(initblk.padr2); \
s->csr[14] = le16_to_cpu(initblk.padr3); \
s->rdra = PHYSADDR(s,initblk.rdra); \
s->tdra = PHYSADDR(s,initblk.tdra); \
} while (0)
if (BCR_SSIZE32(s)) {
struct pcnet_initblk32 initblk;
PCNET_INIT();
#ifdef PCNET_DEBUG
printf("initblk.rlen=0x%02x, initblk.tlen=0x%02x\n",
initblk.rlen, initblk.tlen);
#endif
s->phys_mem_read(s->dma_opaque, PHYSADDR(s,CSR_IADR(s)),
(uint8_t *)&initblk, sizeof(initblk));
mode = initblk.mode;
rlen = initblk.rlen >> 4;
tlen = initblk.tlen >> 4;
ladrf = initblk.ladrf;
padr = initblk.padr;
if (CSR_BIGENDIAN(s)) {
rdra = be32_to_cpu(initblk.rdra);
tdra = be32_to_cpu(initblk.tdra);
} else {
rdra = le32_to_cpu(initblk.rdra);
tdra = le32_to_cpu(initblk.tdra);
}
s->rdra = PHYSADDR(s,initblk.rdra);
s->tdra = PHYSADDR(s,initblk.tdra);
} else {
struct pcnet_initblk16 initblk;
PCNET_INIT();
#ifdef PCNET_DEBUG
printf("initblk.rlen=0x%02x, initblk.tlen=0x%02x\n",
initblk.rlen, initblk.tlen);
#endif
s->phys_mem_read(s->dma_opaque, PHYSADDR(s,CSR_IADR(s)),
(uint8_t *)&initblk, sizeof(initblk));
mode = initblk.mode;
ladrf = initblk.ladrf;
padr = initblk.padr;
if (CSR_BIGENDIAN(s)) {
rdra = be32_to_cpu(initblk.rdra);
tdra = be32_to_cpu(initblk.tdra);
} else {
rdra = le32_to_cpu(initblk.rdra);
tdra = le32_to_cpu(initblk.tdra);
}
rlen = rdra >> 29;
tlen = tdra >> 29;
rdra &= 0x00ffffff;
tdra &= 0x00ffffff;
}
#undef PCNET_INIT
#if defined(PCNET_DEBUG)
printf("rlen=%d tlen=%d\n",
rlen, tlen);
#endif
CSR_RCVRL(s) = (rlen < 9) ? (1 << rlen) : 512;
CSR_XMTRL(s) = (tlen < 9) ? (1 << tlen) : 512;
s->csr[ 6] = (tlen << 12) | (rlen << 8);
if (CSR_BIGENDIAN(s)) {
s->csr[15] = be16_to_cpu(mode);
s->csr[ 8] = be16_to_cpu(ladrf[0]);
s->csr[ 9] = be16_to_cpu(ladrf[1]);
s->csr[10] = be16_to_cpu(ladrf[2]);
s->csr[11] = be16_to_cpu(ladrf[3]);
s->csr[12] = be16_to_cpu(padr[0]);
s->csr[13] = be16_to_cpu(padr[1]);
s->csr[14] = be16_to_cpu(padr[2]);
} else {
s->csr[15] = le16_to_cpu(mode);
s->csr[ 8] = le16_to_cpu(ladrf[0]);
s->csr[ 9] = le16_to_cpu(ladrf[1]);
s->csr[10] = le16_to_cpu(ladrf[2]);
s->csr[11] = le16_to_cpu(ladrf[3]);
s->csr[12] = le16_to_cpu(padr[0]);
s->csr[13] = le16_to_cpu(padr[1]);
s->csr[14] = le16_to_cpu(padr[2]);
}
s->rdra = PHYSADDR(s, rdra);
s->tdra = PHYSADDR(s, tdra);
CSR_RCVRC(s) = CSR_RCVRL(s);
CSR_XMTRC(s) = CSR_XMTRL(s);
@ -1035,7 +1107,7 @@ static void pcnet_receive(void *opaque, const uint8_t *buf, int size)
#define PCNET_RECV_STORE() do { \
int count = MIN(4096 - rmd.rmd1.bcnt,size); \
target_phys_addr_t rbadr = PHYSADDR(s, rmd.rmd0.rbadr); \
cpu_physical_memory_write(rbadr, src, count); \
s->phys_mem_write(s->dma_opaque, rbadr, src, count); \
src += count; size -= count; \
rmd.rmd2.mcnt = count; rmd.rmd1.own = 0; \
RMDSTORE(&rmd, PHYSADDR(s,crda)); \
@ -1125,14 +1197,14 @@ static void pcnet_transmit(PCNetState *s)
if (tmd.tmd1.stp) {
s->xmit_pos = 0;
if (!tmd.tmd1.enp) {
cpu_physical_memory_read(PHYSADDR(s, tmd.tmd0.tbadr),
s->phys_mem_read(s->dma_opaque, PHYSADDR(s, tmd.tmd0.tbadr),
s->buffer, 4096 - tmd.tmd1.bcnt);
s->xmit_pos += 4096 - tmd.tmd1.bcnt;
}
xmit_cxda = PHYSADDR(s,CSR_CXDA(s));
}
if (tmd.tmd1.enp && (s->xmit_pos >= 0)) {
cpu_physical_memory_read(PHYSADDR(s, tmd.tmd0.tbadr),
s->phys_mem_read(s->dma_opaque, PHYSADDR(s, tmd.tmd0.tbadr),
s->buffer + s->xmit_pos, 4096 - tmd.tmd1.bcnt);
s->xmit_pos += 4096 - tmd.tmd1.bcnt;
#ifdef PCNET_DEBUG
@ -1426,8 +1498,9 @@ static uint32_t pcnet_bcr_readw(PCNetState *s, uint32_t rap)
return val;
}
static void pcnet_h_reset(PCNetState *s)
void pcnet_h_reset(void *opaque)
{
PCNetState *s = opaque;
int i;
uint16_t checksum;
@ -1703,6 +1776,90 @@ static uint32_t pcnet_mmio_readl(void *opaque, target_phys_addr_t addr)
}
static void pcnet_save(QEMUFile *f, void *opaque)
{
PCNetState *s = opaque;
unsigned int i;
if (s->pci_dev)
pci_device_save(s->pci_dev, f);
qemu_put_be32s(f, &s->rap);
qemu_put_be32s(f, &s->isr);
qemu_put_be32s(f, &s->lnkst);
qemu_put_be32s(f, &s->rdra);
qemu_put_be32s(f, &s->tdra);
qemu_put_buffer(f, s->prom, 16);
for (i = 0; i < 128; i++)
qemu_put_be16s(f, &s->csr[i]);
for (i = 0; i < 32; i++)
qemu_put_be16s(f, &s->bcr[i]);
qemu_put_be64s(f, &s->timer);
qemu_put_be32s(f, &s->xmit_pos);
qemu_put_be32s(f, &s->recv_pos);
qemu_put_buffer(f, s->buffer, 4096);
qemu_put_be32s(f, &s->tx_busy);
qemu_put_timer(f, s->poll_timer);
}
static int pcnet_load(QEMUFile *f, void *opaque, int version_id)
{
PCNetState *s = opaque;
int i, ret;
if (version_id != 2)
return -EINVAL;
if (s->pci_dev) {
ret = pci_device_load(s->pci_dev, f);
if (ret < 0)
return ret;
}
qemu_get_be32s(f, &s->rap);
qemu_get_be32s(f, &s->isr);
qemu_get_be32s(f, &s->lnkst);
qemu_get_be32s(f, &s->rdra);
qemu_get_be32s(f, &s->tdra);
qemu_get_buffer(f, s->prom, 16);
for (i = 0; i < 128; i++)
qemu_get_be16s(f, &s->csr[i]);
for (i = 0; i < 32; i++)
qemu_get_be16s(f, &s->bcr[i]);
qemu_get_be64s(f, &s->timer);
qemu_get_be32s(f, &s->xmit_pos);
qemu_get_be32s(f, &s->recv_pos);
qemu_get_buffer(f, s->buffer, 4096);
qemu_get_be32s(f, &s->tx_busy);
qemu_get_timer(f, s->poll_timer);
return 0;
}
static void pcnet_common_init(PCNetState *d, NICInfo *nd, const char *info_str)
{
d->poll_timer = qemu_new_timer(vm_clock, pcnet_poll_timer, d);
d->nd = nd;
d->vc = qemu_new_vlan_client(nd->vlan, pcnet_receive,
pcnet_can_receive, d);
snprintf(d->vc->info_str, sizeof(d->vc->info_str),
"pcnet macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
d->nd->macaddr[0],
d->nd->macaddr[1],
d->nd->macaddr[2],
d->nd->macaddr[3],
d->nd->macaddr[4],
d->nd->macaddr[5]);
pcnet_h_reset(d);
register_savevm("pcnet", 0, 2, pcnet_save, pcnet_load, d);
}
/* PCI interface */
static CPUWriteMemoryFunc *pcnet_mmio_write[] = {
(CPUWriteMemoryFunc *)&pcnet_mmio_writeb,
(CPUWriteMemoryFunc *)&pcnet_mmio_writew,
@ -1724,7 +1881,26 @@ static void pcnet_mmio_map(PCIDevice *pci_dev, int region_num,
printf("pcnet_ioport_map addr=0x%08x 0x%08x\n", addr, size);
#endif
cpu_register_physical_memory(addr, PCNET_PNPMMIO_SIZE, d->mmio_io_addr);
cpu_register_physical_memory(addr, PCNET_PNPMMIO_SIZE, d->mmio_index);
}
static void pcnet_pci_set_irq_cb(void *opaque, int isr)
{
PCNetState *s = opaque;
pci_set_irq(&s->dev, 0, isr);
}
static void pci_physical_memory_write(void *dma_opaque, target_phys_addr_t addr,
uint8_t *buf, int len)
{
cpu_physical_memory_write(addr, buf, len);
}
static void pci_physical_memory_read(void *dma_opaque, target_phys_addr_t addr,
uint8_t *buf, int len)
{
cpu_physical_memory_read(addr, buf, len);
}
void pci_pcnet_init(PCIBus *bus, NICInfo *nd)
@ -1760,7 +1936,7 @@ void pci_pcnet_init(PCIBus *bus, NICInfo *nd)
pci_conf[0x3f] = 0xff;
/* Handler for memory-mapped I/O */
d->mmio_io_addr =
d->mmio_index =
cpu_register_io_memory(0, pcnet_mmio_read, pcnet_mmio_write, d);
pci_register_io_region((PCIDevice *)d, 0, PCNET_IOPORT_SIZE,
@ -1769,21 +1945,58 @@ void pci_pcnet_init(PCIBus *bus, NICInfo *nd)
pci_register_io_region((PCIDevice *)d, 1, PCNET_PNPMMIO_SIZE,
PCI_ADDRESS_SPACE_MEM, pcnet_mmio_map);
d->poll_timer = qemu_new_timer(vm_clock, pcnet_poll_timer, d);
d->set_irq_cb = pcnet_pci_set_irq_cb;
d->phys_mem_read = pci_physical_memory_read;
d->phys_mem_write = pci_physical_memory_write;
d->pci_dev = &d->dev;
d->nd = nd;
d->vc = qemu_new_vlan_client(nd->vlan, pcnet_receive,
pcnet_can_receive, d);
snprintf(d->vc->info_str, sizeof(d->vc->info_str),
"pcnet macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
d->nd->macaddr[0],
d->nd->macaddr[1],
d->nd->macaddr[2],
d->nd->macaddr[3],
d->nd->macaddr[4],
d->nd->macaddr[5]);
pcnet_h_reset(d);
pcnet_common_init(d, nd, "pcnet");
}
/* SPARC32 interface */
#if defined (TARGET_SPARC) && !defined(TARGET_SPARC64) // Avoid compile failure
static CPUReadMemoryFunc *lance_mem_read[3] = {
(CPUReadMemoryFunc *)&pcnet_ioport_readw,
(CPUReadMemoryFunc *)&pcnet_ioport_readw,
(CPUReadMemoryFunc *)&pcnet_ioport_readw,
};
static CPUWriteMemoryFunc *lance_mem_write[3] = {
(CPUWriteMemoryFunc *)&pcnet_ioport_writew,
(CPUWriteMemoryFunc *)&pcnet_ioport_writew,
(CPUWriteMemoryFunc *)&pcnet_ioport_writew,
};
static void pcnet_sparc_set_irq_cb(void *opaque, int isr)
{
PCNetState *s = opaque;
ledma_set_irq(s->dma_opaque, isr);
}
void *lance_init(NICInfo *nd, uint32_t leaddr, void *dma_opaque)
{
PCNetState *d;
int lance_io_memory;
d = qemu_mallocz(sizeof(PCNetState));
if (!d)
return NULL;
lance_io_memory =
cpu_register_io_memory(0, lance_mem_read, lance_mem_write, d);
d->dma_opaque = dma_opaque;
cpu_register_physical_memory(leaddr, 4, lance_io_memory);
d->set_irq_cb = pcnet_sparc_set_irq_cb;
d->phys_mem_read = ledma_memory_read;
d->phys_mem_write = ledma_memory_write;
pcnet_common_init(d, nd, "lance");
return d;
}
#endif /* TARGET_SPARC */