target/cris: Let cris_mmu_translate() use MMUAccessType access_type
All callers of cris_mmu_translate() provide a MMUAccessType type. Let the prototype use it as argument, as it is stricter than an integer. We can remove the documentation as enum names are self explicit. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <20210128003223.3561108-3-f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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@ -129,10 +129,10 @@ static void dump_tlb(CPUCRISState *env, int mmu)
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}
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}
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#endif
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#endif
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/* rw 0 = read, 1 = write, 2 = exec. */
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static int cris_mmu_translate_page(struct cris_mmu_result *res,
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static int cris_mmu_translate_page(struct cris_mmu_result *res,
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CPUCRISState *env, uint32_t vaddr,
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CPUCRISState *env, uint32_t vaddr,
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int rw, int usermode, int debug)
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MMUAccessType access_type,
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int usermode, int debug)
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{
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{
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unsigned int vpage;
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unsigned int vpage;
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unsigned int idx;
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unsigned int idx;
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@ -151,7 +151,7 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
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r_cfg = env->sregs[SFR_RW_MM_CFG];
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r_cfg = env->sregs[SFR_RW_MM_CFG];
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pid = env->pregs[PR_PID] & 0xff;
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pid = env->pregs[PR_PID] & 0xff;
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switch (rw) {
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switch (access_type) {
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case MMU_INST_FETCH:
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case MMU_INST_FETCH:
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rwcause = CRIS_MMU_ERR_EXEC;
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rwcause = CRIS_MMU_ERR_EXEC;
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mmu = 0;
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mmu = 0;
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@ -219,13 +219,13 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
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vaddr, lo, env->pc));
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vaddr, lo, env->pc));
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match = 0;
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match = 0;
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res->bf_vec = vect_base + 2;
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res->bf_vec = vect_base + 2;
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} else if (rw == MMU_DATA_STORE && cfg_w && !tlb_w) {
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} else if (access_type == MMU_DATA_STORE && cfg_w && !tlb_w) {
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D(printf("tlb: write protected %x lo=%x pc=%x\n",
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D(printf("tlb: write protected %x lo=%x pc=%x\n",
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vaddr, lo, env->pc));
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vaddr, lo, env->pc));
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match = 0;
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match = 0;
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/* write accesses never go through the I mmu. */
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/* write accesses never go through the I mmu. */
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res->bf_vec = vect_base + 3;
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res->bf_vec = vect_base + 3;
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} else if (rw == MMU_INST_FETCH && cfg_x && !tlb_x) {
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} else if (access_type == MMU_INST_FETCH && cfg_x && !tlb_x) {
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D(printf("tlb: exec protected %x lo=%x pc=%x\n",
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D(printf("tlb: exec protected %x lo=%x pc=%x\n",
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vaddr, lo, env->pc));
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vaddr, lo, env->pc));
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match = 0;
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match = 0;
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@ -272,9 +272,9 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
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D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
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D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
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}
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}
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D(printf("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
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D(printf("%s access=%u mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
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" %x cause=%x sel=%x sp=%x %x %x\n",
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" %x cause=%x sel=%x sp=%x %x %x\n",
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__func__, rw, match, env->pc,
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__func__, access_type, match, env->pc,
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vaddr, vpage,
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vaddr, vpage,
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tlb_vpn, tlb_pfn, tlb_pid,
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tlb_vpn, tlb_pfn, tlb_pid,
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pid,
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pid,
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@ -319,8 +319,8 @@ void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
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}
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}
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int cris_mmu_translate(struct cris_mmu_result *res,
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int cris_mmu_translate(struct cris_mmu_result *res,
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CPUCRISState *env, uint32_t vaddr,
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CPUCRISState *env, uint32_t vaddr,
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int rw, int mmu_idx, int debug)
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MMUAccessType access_type, int mmu_idx, int debug)
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{
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{
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int seg;
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int seg;
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int miss = 0;
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int miss = 0;
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@ -329,7 +329,7 @@ int cris_mmu_translate(struct cris_mmu_result *res,
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old_srs = env->pregs[PR_SRS];
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old_srs = env->pregs[PR_SRS];
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env->pregs[PR_SRS] = rw == MMU_INST_FETCH ? 1 : 2;
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env->pregs[PR_SRS] = access_type == MMU_INST_FETCH ? 1 : 2;
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if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
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if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
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res->phy = vaddr;
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res->phy = vaddr;
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@ -346,7 +346,7 @@ int cris_mmu_translate(struct cris_mmu_result *res,
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res->phy = base | (0x0fffffff & vaddr);
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res->phy = base | (0x0fffffff & vaddr);
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res->prot = PAGE_BITS;
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res->prot = PAGE_BITS;
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} else {
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} else {
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miss = cris_mmu_translate_page(res, env, vaddr, rw,
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miss = cris_mmu_translate_page(res, env, vaddr, access_type,
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is_user, debug);
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is_user, debug);
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}
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}
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done:
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done:
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@ -17,6 +17,6 @@ void cris_mmu_init(CPUCRISState *env);
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void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid);
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void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid);
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int cris_mmu_translate(struct cris_mmu_result *res,
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int cris_mmu_translate(struct cris_mmu_result *res,
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CPUCRISState *env, uint32_t vaddr,
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CPUCRISState *env, uint32_t vaddr,
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int rw, int mmu_idx, int debug);
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MMUAccessType access_type, int mmu_idx, int debug);
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#endif
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#endif
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