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target-xtensa: mark reserved and TBD opcodes

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Reserved opcodes must generate illegal instruction exception. Usually
they signal emulation quality problems.
Not implemented opcodes are good to see.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Max Filippov 2011-09-06 03:55:37 +04:00 committed by Blue Swirl
parent 809377aa52
commit 91a5bb76d4
1 changed files with 109 additions and 1 deletions
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110
target-xtensa/translate.c
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@ -267,6 +267,14 @@ static void disas_xtensa_insn(DisasContext *dc)
} \ } \
} while (0) } while (0)
#define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
#define RESERVED() do { \
qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
dc->pc, b0, b1, b2, __FILE__, __LINE__); \
goto invalid_opcode; \
} while (0)
#ifdef TARGET_WORDS_BIGENDIAN #ifdef TARGET_WORDS_BIGENDIAN
#define OP0 (((b0) & 0xf0) >> 4) #define OP0 (((b0) & 0xf0) >> 4)
#define OP1 (((b2) & 0xf0) >> 4) #define OP1 (((b2) & 0xf0) >> 4)
@ -367,9 +375,11 @@ static void disas_xtensa_insn(DisasContext *dc)
case 0: /*SNM0*/ case 0: /*SNM0*/
switch (CALLX_M) { switch (CALLX_M) {
case 0: /*ILL*/ case 0: /*ILL*/
TBD();
break; break;
case 1: /*reserved*/ case 1: /*reserved*/
RESERVED();
break; break;
case 2: /*JR*/ case 2: /*JR*/
@ -381,9 +391,11 @@ static void disas_xtensa_insn(DisasContext *dc)
case 1: /*RETWw*/ case 1: /*RETWw*/
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
TBD();
break; break;
case 3: /*reserved*/ case 3: /*reserved*/
RESERVED();
break; break;
} }
break; break;
@ -404,6 +416,7 @@ static void disas_xtensa_insn(DisasContext *dc)
case 2: /*CALLX8w*/ case 2: /*CALLX8w*/
case 3: /*CALLX12w*/ case 3: /*CALLX12w*/
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
TBD();
break; break;
} }
break; break;
@ -412,12 +425,59 @@ static void disas_xtensa_insn(DisasContext *dc)
case 1: /*MOVSPw*/ case 1: /*MOVSPw*/
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
TBD();
break; break;
case 2: /*SYNC*/ case 2: /*SYNC*/
TBD();
break; break;
case 3: case 3: /*RFEIx*/
TBD();
break;
case 4: /*BREAKx*/
HAS_OPTION(XTENSA_OPTION_EXCEPTION);
TBD();
break;
case 5: /*SYSCALLx*/
HAS_OPTION(XTENSA_OPTION_EXCEPTION);
TBD();
break;
case 6: /*RSILx*/
HAS_OPTION(XTENSA_OPTION_INTERRUPT);
TBD();
break;
case 7: /*WAITIx*/
HAS_OPTION(XTENSA_OPTION_INTERRUPT);
TBD();
break;
case 8: /*ANY4p*/
HAS_OPTION(XTENSA_OPTION_BOOLEAN);
TBD();
break;
case 9: /*ALL4p*/
HAS_OPTION(XTENSA_OPTION_BOOLEAN);
TBD();
break;
case 10: /*ANY8p*/
HAS_OPTION(XTENSA_OPTION_BOOLEAN);
TBD();
break;
case 11: /*ALL8p*/
HAS_OPTION(XTENSA_OPTION_BOOLEAN);
TBD();
break;
default: /*reserved*/
RESERVED();
break; break;
} }
@ -473,13 +533,16 @@ static void disas_xtensa_insn(DisasContext *dc)
break; break;
case 6: /*RER*/ case 6: /*RER*/
TBD();
break; break;
case 7: /*WER*/ case 7: /*WER*/
TBD();
break; break;
case 8: /*ROTWw*/ case 8: /*ROTWw*/
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
TBD();
break; break;
case 14: /*NSAu*/ case 14: /*NSAu*/
@ -493,11 +556,13 @@ static void disas_xtensa_insn(DisasContext *dc)
break; break;
default: /*reserved*/ default: /*reserved*/
RESERVED();
break; break;
} }
break; break;
case 5: /*TLB*/ case 5: /*TLB*/
TBD();
break; break;
case 6: /*RT0*/ case 6: /*RT0*/
@ -518,11 +583,13 @@ static void disas_xtensa_insn(DisasContext *dc)
break; break;
default: /*reserved*/ default: /*reserved*/
RESERVED();
break; break;
} }
break; break;
case 7: /*reserved*/ case 7: /*reserved*/
RESERVED();
break; break;
case 8: /*ADD*/ case 8: /*ADD*/
@ -582,6 +649,9 @@ static void disas_xtensa_insn(DisasContext *dc)
gen_rsr(dc, cpu_R[RRR_T], RSR_SR); gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
gen_wsr(dc, RSR_SR, tmp); gen_wsr(dc, RSR_SR, tmp);
tcg_temp_free(tmp); tcg_temp_free(tmp);
if (!sregnames[RSR_SR]) {
TBD();
}
} }
break; break;
@ -671,21 +741,29 @@ static void disas_xtensa_insn(DisasContext *dc)
break; break;
default: /*reserved*/ default: /*reserved*/
RESERVED();
break; break;
} }
break; break;
case 2: /*RST2*/ case 2: /*RST2*/
TBD();
break; break;
case 3: /*RST3*/ case 3: /*RST3*/
switch (OP2) { switch (OP2) {
case 0: /*RSR*/ case 0: /*RSR*/
gen_rsr(dc, cpu_R[RRR_T], RSR_SR); gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
if (!sregnames[RSR_SR]) {
TBD();
}
break; break;
case 1: /*WSR*/ case 1: /*WSR*/
gen_wsr(dc, RSR_SR, cpu_R[RRR_T]); gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
if (!sregnames[RSR_SR]) {
TBD();
}
break; break;
case 2: /*SEXTu*/ case 2: /*SEXTu*/
@ -778,10 +856,12 @@ static void disas_xtensa_insn(DisasContext *dc)
case 12: /*MOVFp*/ case 12: /*MOVFp*/
HAS_OPTION(XTENSA_OPTION_BOOLEAN); HAS_OPTION(XTENSA_OPTION_BOOLEAN);
TBD();
break; break;
case 13: /*MOVTp*/ case 13: /*MOVTp*/
HAS_OPTION(XTENSA_OPTION_BOOLEAN); HAS_OPTION(XTENSA_OPTION_BOOLEAN);
TBD();
break; break;
case 14: /*RUR*/ case 14: /*RUR*/
@ -791,6 +871,7 @@ static void disas_xtensa_insn(DisasContext *dc)
tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]); tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
} else { } else {
qemu_log("RUR %d not implemented, ", st); qemu_log("RUR %d not implemented, ", st);
TBD();
} }
} }
break; break;
@ -801,6 +882,7 @@ static void disas_xtensa_insn(DisasContext *dc)
tcg_gen_mov_i32(cpu_UR[RSR_SR], cpu_R[RRR_T]); tcg_gen_mov_i32(cpu_UR[RSR_SR], cpu_R[RRR_T]);
} else { } else {
qemu_log("WUR %d not implemented, ", RSR_SR); qemu_log("WUR %d not implemented, ", RSR_SR);
TBD();
} }
} }
break; break;
@ -822,27 +904,34 @@ static void disas_xtensa_insn(DisasContext *dc)
break; break;
case 6: /*CUST0*/ case 6: /*CUST0*/
RESERVED();
break; break;
case 7: /*CUST1*/ case 7: /*CUST1*/
RESERVED();
break; break;
case 8: /*LSCXp*/ case 8: /*LSCXp*/
HAS_OPTION(XTENSA_OPTION_COPROCESSOR); HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
TBD();
break; break;
case 9: /*LSC4*/ case 9: /*LSC4*/
TBD();
break; break;
case 10: /*FP0*/ case 10: /*FP0*/
HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
TBD();
break; break;
case 11: /*FP1*/ case 11: /*FP1*/
HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
TBD();
break; break;
default: /*reserved*/ default: /*reserved*/
RESERVED();
break; break;
} }
break; break;
@ -894,6 +983,7 @@ static void disas_xtensa_insn(DisasContext *dc)
break; break;
case 7: /*CACHEc*/ case 7: /*CACHEc*/
TBD();
break; break;
case 9: /*L16SI*/ case 9: /*L16SI*/
@ -946,6 +1036,7 @@ static void disas_xtensa_insn(DisasContext *dc)
break; break;
default: /*reserved*/ default: /*reserved*/
RESERVED();
break; break;
} }
break; break;
@ -953,10 +1044,12 @@ static void disas_xtensa_insn(DisasContext *dc)
case 3: /*LSCIp*/ case 3: /*LSCIp*/
HAS_OPTION(XTENSA_OPTION_COPROCESSOR); HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
TBD();
break; break;
case 4: /*MAC16d*/ case 4: /*MAC16d*/
HAS_OPTION(XTENSA_OPTION_MAC16); HAS_OPTION(XTENSA_OPTION_MAC16);
TBD();
break; break;
case 5: /*CALLN*/ case 5: /*CALLN*/
@ -970,6 +1063,7 @@ static void disas_xtensa_insn(DisasContext *dc)
case 2: /*CALL8w*/ case 2: /*CALL8w*/
case 3: /*CALL12w*/ case 3: /*CALL12w*/
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
TBD();
break; break;
} }
break; break;
@ -1012,28 +1106,35 @@ static void disas_xtensa_insn(DisasContext *dc)
switch (BRI8_M) { switch (BRI8_M) {
case 0: /*ENTRYw*/ case 0: /*ENTRYw*/
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
TBD();
break; break;
case 1: /*B1*/ case 1: /*B1*/
switch (BRI8_R) { switch (BRI8_R) {
case 0: /*BFp*/ case 0: /*BFp*/
HAS_OPTION(XTENSA_OPTION_BOOLEAN); HAS_OPTION(XTENSA_OPTION_BOOLEAN);
TBD();
break; break;
case 1: /*BTp*/ case 1: /*BTp*/
HAS_OPTION(XTENSA_OPTION_BOOLEAN); HAS_OPTION(XTENSA_OPTION_BOOLEAN);
TBD();
break; break;
case 8: /*LOOP*/ case 8: /*LOOP*/
TBD();
break; break;
case 9: /*LOOPNEZ*/ case 9: /*LOOPNEZ*/
TBD();
break; break;
case 10: /*LOOPGTZ*/ case 10: /*LOOPGTZ*/
TBD();
break; break;
default: /*reserved*/ default: /*reserved*/
RESERVED();
break; break;
} }
@ -1169,28 +1270,35 @@ static void disas_xtensa_insn(DisasContext *dc)
break; break;
case 1: /*RETW.Nn*/ case 1: /*RETW.Nn*/
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
TBD();
break; break;
case 2: /*BREAK.Nn*/ case 2: /*BREAK.Nn*/
TBD();
break; break;
case 3: /*NOP.Nn*/ case 3: /*NOP.Nn*/
break; break;
case 6: /*ILL.Nn*/ case 6: /*ILL.Nn*/
TBD();
break; break;
default: /*reserved*/ default: /*reserved*/
RESERVED();
break; break;
} }
break; break;
default: /*reserved*/ default: /*reserved*/
RESERVED();
break; break;
} }
break; break;
default: /*reserved*/ default: /*reserved*/
RESERVED();
break; break;
} }