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target/ppc: cpu_init: Expose some SPR registration helpers

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The following patches will move CPU-specific code into separate files,
so expose the most used SPR registration functions:

register_sdr1_sprs         | 22 callers
register_low_BATs          | 20 callers
register_non_embedded_sprs | 19 callers
register_high_BATs         | 10 callers
register_thrm_sprs         | 8 callers
register_usprgh_sprs       | 6 callers
register_6xx_7xx_soft_tlb  | only 3 callers, but it helps to
                             keep the soft TLB code consistent.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-25-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Fabiano Rosas 2022-02-18 08:34:15 +01:00 committed by Cédric Le Goater
parent 99e964ef95
commit 917ea4381a
2 changed files with 15 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
target/ppc/cpu_init.c
View File

@ -241,7 +241,7 @@ static void register_generic_sprs(PowerPCCPU *cpu)
0x00000000); 0x00000000);
} }
static void register_non_embedded_sprs(CPUPPCState *env) void register_non_embedded_sprs(CPUPPCState *env)
{ {
/* Exception processing */ /* Exception processing */
spr_register_kvm(env, SPR_DSISR, "DSISR", spr_register_kvm(env, SPR_DSISR, "DSISR",
@ -260,7 +260,7 @@ static void register_non_embedded_sprs(CPUPPCState *env)
} }
/* Storage Description Register 1 */ /* Storage Description Register 1 */
static void register_sdr1_sprs(CPUPPCState *env) void register_sdr1_sprs(CPUPPCState *env)
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
if (env->has_hv_mode) { if (env->has_hv_mode) {
@ -283,7 +283,7 @@ static void register_sdr1_sprs(CPUPPCState *env)
} }
/* BATs 0-3 */ /* BATs 0-3 */
static void register_low_BATs(CPUPPCState *env) void register_low_BATs(CPUPPCState *env)
{ {
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
spr_register(env, SPR_IBAT0U, "IBAT0U", spr_register(env, SPR_IBAT0U, "IBAT0U",
@ -355,7 +355,7 @@ static void register_low_BATs(CPUPPCState *env)
} }
/* BATs 4-7 */ /* BATs 4-7 */
static void register_high_BATs(CPUPPCState *env) void register_high_BATs(CPUPPCState *env)
{ {
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
spr_register(env, SPR_IBAT4U, "IBAT4U", spr_register(env, SPR_IBAT4U, "IBAT4U",
@ -427,7 +427,7 @@ static void register_high_BATs(CPUPPCState *env)
} }
/* Softare table search registers */ /* Softare table search registers */
static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
{ {
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
env->nb_tlb = nb_tlbs; env->nb_tlb = nb_tlbs;
@ -667,7 +667,7 @@ static void register_iamr_sprs(CPUPPCState *env)
} }
#endif /* TARGET_PPC64 */ #endif /* TARGET_PPC64 */
static void register_thrm_sprs(CPUPPCState *env) void register_thrm_sprs(CPUPPCState *env)
{ {
/* Thermal management */ /* Thermal management */
spr_register(env, SPR_THRM1, "THRM1", spr_register(env, SPR_THRM1, "THRM1",
@ -1072,7 +1072,7 @@ static void register_l3_ctrl(CPUPPCState *env)
0x00000000); 0x00000000);
} }
static void register_usprgh_sprs(CPUPPCState *env) void register_usprgh_sprs(CPUPPCState *env)
{ {
spr_register(env, SPR_USPRG4, "USPRG4", spr_register(env, SPR_USPRG4, "USPRG4",
&spr_read_ureg, SPR_NOACCESS, &spr_read_ureg, SPR_NOACCESS,

8
target/ppc/spr_common.h
View File

@ -141,4 +141,12 @@ void spr_write_hmer(DisasContext *ctx, int sprn, int gprn);
void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn); void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn);
#endif #endif
void register_low_BATs(CPUPPCState *env);
void register_high_BATs(CPUPPCState *env);
void register_sdr1_sprs(CPUPPCState *env);
void register_thrm_sprs(CPUPPCState *env);
void register_usprgh_sprs(CPUPPCState *env);
void register_non_embedded_sprs(CPUPPCState *env);
void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways);
#endif #endif