target/riscv: Adjust privilege level for HLV(X)/HSV instructions
According to the specification the "field SPVP of hstatus controls the privilege level of the access" for the hypervisor virtual-machine load and store instructions HLV, HLVX and HSV. Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -368,7 +368,11 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
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use_background = true;
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}
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if (mode == PRV_M && access_type != MMU_INST_FETCH) {
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/* MPRV does not affect the virtual-machine load/store
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instructions, HLV, HLVX, and HSV. */
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if (riscv_cpu_two_stage_lookup(mmu_idx)) {
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mode = get_field(env->hstatus, HSTATUS_SPVP);
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} else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
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if (get_field(env->mstatus, MSTATUS_MPRV)) {
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mode = get_field(env->mstatus, MSTATUS_MPP);
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}
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@ -741,18 +745,17 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
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__func__, address, access_type, mmu_idx);
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if (mode == PRV_M && access_type != MMU_INST_FETCH) {
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if (get_field(env->mstatus, MSTATUS_MPRV)) {
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/* MPRV does not affect the virtual-machine load/store
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instructions, HLV, HLVX, and HSV. */
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if (riscv_cpu_two_stage_lookup(mmu_idx)) {
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mode = get_field(env->hstatus, HSTATUS_SPVP);
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} else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
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get_field(env->mstatus, MSTATUS_MPRV)) {
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mode = get_field(env->mstatus, MSTATUS_MPP);
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}
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}
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if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
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access_type != MMU_INST_FETCH &&
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get_field(env->mstatus, MSTATUS_MPRV) &&
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get_field(env->mstatus, MSTATUS_MPV)) {
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if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
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two_stage_lookup = true;
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}
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}
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if (riscv_cpu_virt_enabled(env) ||
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((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
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