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target/riscv: Adjust privilege level for HLV(X)/HSV instructions

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According to the specification the "field SPVP of hstatus controls the
privilege level of the access" for the hypervisor virtual-machine load
and store instructions HLV, HLVX and HSV.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Georg Kotheimer 2021-03-11 11:30:05 +01:00 committed by Alistair Francis
parent 2c2e0f2842
commit 90ec1cff76
1 changed files with 14 additions and 11 deletions
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23
target/riscv/cpu_helper.c
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@ -368,7 +368,11 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
use_background = true; use_background = true;
} }
if (mode == PRV_M && access_type != MMU_INST_FETCH) { /* MPRV does not affect the virtual-machine load/store
instructions, HLV, HLVX, and HSV. */
if (riscv_cpu_two_stage_lookup(mmu_idx)) {
mode = get_field(env->hstatus, HSTATUS_SPVP);
} else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
if (get_field(env->mstatus, MSTATUS_MPRV)) { if (get_field(env->mstatus, MSTATUS_MPRV)) {
mode = get_field(env->mstatus, MSTATUS_MPP); mode = get_field(env->mstatus, MSTATUS_MPP);
} }
@ -741,18 +745,17 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
__func__, address, access_type, mmu_idx); __func__, address, access_type, mmu_idx);
if (mode == PRV_M && access_type != MMU_INST_FETCH) { /* MPRV does not affect the virtual-machine load/store
if (get_field(env->mstatus, MSTATUS_MPRV)) { instructions, HLV, HLVX, and HSV. */
if (riscv_cpu_two_stage_lookup(mmu_idx)) {
mode = get_field(env->hstatus, HSTATUS_SPVP);
} else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
get_field(env->mstatus, MSTATUS_MPRV)) {
mode = get_field(env->mstatus, MSTATUS_MPP); mode = get_field(env->mstatus, MSTATUS_MPP);
} if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) {
}
if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
access_type != MMU_INST_FETCH &&
get_field(env->mstatus, MSTATUS_MPRV) &&
get_field(env->mstatus, MSTATUS_MPV)) {
two_stage_lookup = true; two_stage_lookup = true;
} }
}
if (riscv_cpu_virt_enabled(env) || if (riscv_cpu_virt_enabled(env) ||
((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&