tb hash: track translated blocks with qht
Having a fixed-size hash table for keeping track of all translation blocks
is suboptimal: some workloads are just too big or too small to get maximum
performance from the hash table. The MRU promotion policy helps improve
performance when the hash table is a little undersized, but it cannot
make up for severely undersized hash tables.
Furthermore, frequent MRU promotions result in writes that are a scalability
bottleneck. For scalability, lookups should only perform reads, not writes.
This is not a big deal for now, but it will become one once MTTCG matures.
The appended fixes these issues by using qht as the implementation of
the TB hash table. This solution is superior to other alternatives considered,
namely:
- master: implementation in QEMU before this patchset
- xxhash: before this patch, i.e. fixed buckets + xxhash hashing + MRU.
- xxhash-rcu: fixed buckets + xxhash + RCU list + MRU.
MRU is implemented here by adding an intermediate struct
that contains the u32 hash and a pointer to the TB; this
allows us, on an MRU promotion, to copy said struct (that is not
at the head), and put this new copy at the head. After a grace
period, the original non-head struct can be eliminated, and
after another grace period, freed.
- qht-fixed-nomru: fixed buckets + xxhash + qht without auto-resize +
no MRU for lookups; MRU for inserts.
The appended solution is the following:
- qht-dyn-nomru: dynamic number of buckets + xxhash + qht w/ auto-resize +
no MRU for lookups; MRU for inserts.
The plots below compare the considered solutions. The Y axis shows the
boot time (in seconds) of a debian jessie image with arm-softmmu; the X axis
sweeps the number of buckets (or initial number of buckets for qht-autoresize).
The plots in PNG format (and with errorbars) can be seen here:
http://imgur.com/a/Awgnq
Each test runs 5 times, and the entire QEMU process is pinned to a
single core for repeatability of results.
Host: Intel Xeon E5-2690
28 ++------------+-------------+-------------+-------------+------------++
A***** + + + master **A*** +
27 ++ * xxhash ##B###++
| A******A****** xxhash-rcu $$C$$$ |
26 C$$ A******A****** qht-fixed-nomru*%%D%%%++
D%%$$ A******A******A*qht-dyn-mru A*E****A
25 ++ %%$$ qht-dyn-nomru &&F&&&++
B#####% |
24 ++ #C$$$$$ ++
| B### $ |
| ## C$$$$$$ |
23 ++ # C$$$$$$ ++
| B###### C$$$$$$ %%%D
22 ++ %B###### C$$$$$$C$$$$$$C$$$$$$C$$$$$$C$$$$$$C
| D%%%%%%B###### @E@@@@@@ %%%D%%%@@@E@@@@@@E
21 E@@@@@@E@@@@@@F&&&@@@E@@@&&&D%%%%%%B######B######B######B######B######B
+ E@@@ F&&& + E@ + F&&& + +
20 ++------------+-------------+-------------+-------------+------------++
14 16 18 20 22 24
log2 number of buckets
Host: Intel i7-4790K
14.5 ++------------+------------+-------------+------------+------------++
A** + + + master **A*** +
14 ++ ** xxhash ##B###++
13.5 ++ ** xxhash-rcu $$C$$$++
| qht-fixed-nomru %%D%%% |
13 ++ A****** qht-dyn-mru @@E@@@++
| A*****A******A****** qht-dyn-nomru &&F&&& |
12.5 C$$ A******A******A*****A****** ***A
12 ++ $$ A*** ++
D%%% $$ |
11.5 ++ %% ++
B### %C$$$$$$ |
11 ++ ## D%%%%% C$$$$$ ++
| # % C$$$$$$ |
10.5 F&&&&&&B######D%%%%% C$$$$$$C$$$$$$C$$$$$$C$$$$$C$$$$$$ $$$C
10 E@@@@@@E@@@@@@B#####B######B######E@@@@@@E@@@%%%D%%%%%D%%%###B######B
+ F&& D%%%%%%B######B######B#####B###@@@D%%% +
9.5 ++------------+------------+-------------+------------+------------++
14 16 18 20 22 24
log2 number of buckets
Note that the original point before this patch series is X=15 for "master";
the little sensitivity to the increased number of buckets is due to the
poor hashing function in master.
xxhash-rcu has significant overhead due to the constant churn of allocating
and deallocating intermediate structs for implementing MRU. An alternative
would be do consider failed lookups as "maybe not there", and then
acquire the external lock (tb_lock in this case) to really confirm that
there was indeed a failed lookup. This, however, would not be enough
to implement dynamic resizing--this is more complex: see
"Resizable, Scalable, Concurrent Hash Tables via Relativistic
Programming" by Triplett, McKenney and Walpole. This solution was
discarded due to the very coarse RCU read critical sections that we have
in MTTCG; resizing requires waiting for readers after every pointer update,
and resizes require many pointer updates, so this would quickly become
prohibitive.
qht-fixed-nomru shows that MRU promotion is advisable for undersized
hash tables.
However, qht-dyn-mru shows that MRU promotion is not important if the
hash table is properly sized: there is virtually no difference in
performance between qht-dyn-nomru and qht-dyn-mru.
Before this patch, we're at X=15 on "xxhash"; after this patch, we're at
X=15 @ qht-dyn-nomru. This patch thus matches the best performance that we
can achieve with optimum sizing of the hash table, while keeping the hash
table scalable for readers.
The improvement we get before and after this patch for booting debian jessie
with arm-softmmu is:
- Intel Xeon E5-2690: 10.5% less time
- Intel i7-4790K: 5.2% less time
We could get this same improvement _for this particular workload_ by
statically increasing the size of the hash table. But this would hurt
workloads that do not need a large hash table. The dynamic (upward)
resizing allows us to start small and enlarge the hash table as needed.
A quick note on downsizing: the table is resized back to 2**15 buckets
on every tb_flush; this makes sense because it is not guaranteed that the
table will reach the same number of TBs later on (e.g. most bootup code is
thrown away after boot); it makes sense to grow the hash table as
more code blocks are translated. This also avoids the complication of
having to build downsizing hysteresis logic into qht.
Reviewed-by: Sergey Fedorov <serge.fedorov@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Message-Id: <1465412133-3029-15-git-send-email-cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Emilio G. Cota
Richard Henderson
parent
896a9ee967
commit
909eaac9bb
86
cpu-exec.c
86
cpu-exec.c
@ -225,57 +225,57 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cycles,
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}
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#endif
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struct tb_desc {
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target_ulong pc;
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target_ulong cs_base;
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CPUArchState *env;
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tb_page_addr_t phys_page1;
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uint32_t flags;
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};
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static bool tb_cmp(const void *p, const void *d)
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{
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const TranslationBlock *tb = p;
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const struct tb_desc *desc = d;
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if (tb->pc == desc->pc &&
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tb->page_addr[0] == desc->phys_page1 &&
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tb->cs_base == desc->cs_base &&
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tb->flags == desc->flags) {
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/* check next page if needed */
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if (tb->page_addr[1] == -1) {
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return true;
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} else {
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tb_page_addr_t phys_page2;
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target_ulong virt_page2;
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virt_page2 = (desc->pc & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
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phys_page2 = get_page_addr_code(desc->env, virt_page2);
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if (tb->page_addr[1] == phys_page2) {
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return true;
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}
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}
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}
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return false;
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}
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static TranslationBlock *tb_find_physical(CPUState *cpu,
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target_ulong pc,
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target_ulong cs_base,
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uint32_t flags)
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{
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CPUArchState *env = (CPUArchState *)cpu->env_ptr;
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TranslationBlock *tb, **tb_hash_head, **ptb1;
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tb_page_addr_t phys_pc;
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struct tb_desc desc;
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uint32_t h;
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tb_page_addr_t phys_pc, phys_page1;
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/* find translated block using physical mappings */
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phys_pc = get_page_addr_code(env, pc);
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phys_page1 = phys_pc & TARGET_PAGE_MASK;
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desc.env = (CPUArchState *)cpu->env_ptr;
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desc.cs_base = cs_base;
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desc.flags = flags;
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desc.pc = pc;
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phys_pc = get_page_addr_code(desc.env, pc);
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desc.phys_page1 = phys_pc & TARGET_PAGE_MASK;
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h = tb_hash_func(phys_pc, pc, flags);
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/* Start at head of the hash entry */
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ptb1 = tb_hash_head = &tcg_ctx.tb_ctx.tb_phys_hash[h];
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tb = *ptb1;
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while (tb) {
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if (tb->pc == pc &&
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tb->page_addr[0] == phys_page1 &&
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tb->cs_base == cs_base &&
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tb->flags == flags) {
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if (tb->page_addr[1] == -1) {
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/* done, we have a match */
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break;
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} else {
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/* check next page if needed */
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target_ulong virt_page2 = (pc & TARGET_PAGE_MASK) +
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TARGET_PAGE_SIZE;
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tb_page_addr_t phys_page2 = get_page_addr_code(env, virt_page2);
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if (tb->page_addr[1] == phys_page2) {
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break;
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}
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}
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}
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ptb1 = &tb->phys_hash_next;
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tb = *ptb1;
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}
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if (tb) {
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/* Move the TB to the head of the list */
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*ptb1 = tb->phys_hash_next;
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tb->phys_hash_next = *tb_hash_head;
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*tb_hash_head = tb;
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}
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return tb;
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return qht_lookup(&tcg_ctx.tb_ctx.htable, tb_cmp, &desc, h);
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}
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static TranslationBlock *tb_find_slow(CPUState *cpu,
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@ -215,8 +215,6 @@ struct TranslationBlock {
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void *tc_ptr; /* pointer to the translated code */
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uint8_t *tc_search; /* pointer to search data */
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/* next matching tb for physical address. */
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struct TranslationBlock *phys_hash_next;
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/* original tb when cflags has CF_NOCACHE */
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struct TranslationBlock *orig_tb;
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/* first and second physical page containing code. The lower bit
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@ -21,9 +21,10 @@
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#define QEMU_TB_CONTEXT_H_
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#include "qemu/thread.h"
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#include "qemu/qht.h"
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#define CODE_GEN_PHYS_HASH_BITS 15
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#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
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#define CODE_GEN_HTABLE_BITS 15
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#define CODE_GEN_HTABLE_SIZE (1 << CODE_GEN_HTABLE_BITS)
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typedef struct TranslationBlock TranslationBlock;
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typedef struct TBContext TBContext;
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@ -31,7 +32,7 @@ typedef struct TBContext TBContext;
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struct TBContext {
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TranslationBlock *tbs;
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TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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struct qht htable;
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int nb_tbs;
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/* any access to the tbs or the page table must use this lock */
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QemuMutex tb_lock;
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@ -20,7 +20,6 @@
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#ifndef EXEC_TB_HASH
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#define EXEC_TB_HASH
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#include "exec/exec-all.h"
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#include "exec/tb-hash-xx.h"
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/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
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@ -49,7 +48,7 @@ static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
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static inline
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uint32_t tb_hash_func(tb_page_addr_t phys_pc, target_ulong pc, uint32_t flags)
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{
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return tb_hash_func5(phys_pc, pc, flags) & (CODE_GEN_PHYS_HASH_SIZE - 1);
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return tb_hash_func5(phys_pc, pc, flags);
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}
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#endif
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@ -735,6 +735,13 @@ static inline void code_gen_alloc(size_t tb_size)
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qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
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}
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static void tb_htable_init(void)
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{
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unsigned int mode = QHT_MODE_AUTO_RESIZE;
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qht_init(&tcg_ctx.tb_ctx.htable, CODE_GEN_HTABLE_SIZE, mode);
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}
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/* Must be called before using the QEMU cpus. 'tb_size' is the size
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(in bytes) allocated to the translation buffer. Zero means default
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size. */
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@ -742,6 +749,7 @@ void tcg_exec_init(unsigned long tb_size)
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{
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cpu_gen_init();
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page_init();
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tb_htable_init();
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code_gen_alloc(tb_size);
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#if defined(CONFIG_SOFTMMU)
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/* There's no guest base to take into account, so go ahead and
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@ -846,7 +854,7 @@ void tb_flush(CPUState *cpu)
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cpu->tb_flushed = true;
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}
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memset(tcg_ctx.tb_ctx.tb_phys_hash, 0, sizeof(tcg_ctx.tb_ctx.tb_phys_hash));
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qht_reset_size(&tcg_ctx.tb_ctx.htable, CODE_GEN_HTABLE_SIZE);
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page_flush_tb();
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tcg_ctx.code_gen_ptr = tcg_ctx.code_gen_buffer;
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@ -857,60 +865,46 @@ void tb_flush(CPUState *cpu)
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#ifdef DEBUG_TB_CHECK
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static void tb_invalidate_check(target_ulong address)
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static void
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do_tb_invalidate_check(struct qht *ht, void *p, uint32_t hash, void *userp)
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{
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TranslationBlock *tb;
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int i;
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TranslationBlock *tb = p;
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target_ulong addr = *(target_ulong *)userp;
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address &= TARGET_PAGE_MASK;
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for (i = 0; i < CODE_GEN_PHYS_HASH_SIZE; i++) {
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for (tb = tcg_ctx.tb_ctx.tb_phys_hash[i]; tb != NULL;
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tb = tb->phys_hash_next) {
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if (!(address + TARGET_PAGE_SIZE <= tb->pc ||
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address >= tb->pc + tb->size)) {
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if (!(addr + TARGET_PAGE_SIZE <= tb->pc || addr >= tb->pc + tb->size)) {
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printf("ERROR invalidate: address=" TARGET_FMT_lx
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" PC=%08lx size=%04x\n",
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address, (long)tb->pc, tb->size);
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}
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}
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" PC=%08lx size=%04x\n", addr, (long)tb->pc, tb->size);
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}
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}
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/* verify that all the pages have correct rights for code */
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static void tb_page_check(void)
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static void tb_invalidate_check(target_ulong address)
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{
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TranslationBlock *tb;
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int i, flags1, flags2;
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address &= TARGET_PAGE_MASK;
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qht_iter(&tcg_ctx.tb_ctx.htable, do_tb_invalidate_check, &address);
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}
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static void
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do_tb_page_check(struct qht *ht, void *p, uint32_t hash, void *userp)
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{
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TranslationBlock *tb = p;
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int flags1, flags2;
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for (i = 0; i < CODE_GEN_PHYS_HASH_SIZE; i++) {
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for (tb = tcg_ctx.tb_ctx.tb_phys_hash[i]; tb != NULL;
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tb = tb->phys_hash_next) {
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flags1 = page_get_flags(tb->pc);
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flags2 = page_get_flags(tb->pc + tb->size - 1);
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if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) {
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printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
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(long)tb->pc, tb->size, flags1, flags2);
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}
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}
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}
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}
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/* verify that all the pages have correct rights for code */
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static void tb_page_check(void)
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{
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qht_iter(&tcg_ctx.tb_ctx.htable, do_tb_page_check, NULL);
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}
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#endif
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static inline void tb_hash_remove(TranslationBlock **ptb, TranslationBlock *tb)
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{
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TranslationBlock *tb1;
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for (;;) {
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tb1 = *ptb;
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if (tb1 == tb) {
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*ptb = tb1->phys_hash_next;
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break;
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}
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ptb = &tb1->phys_hash_next;
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}
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}
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static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb)
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{
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TranslationBlock *tb1;
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@ -998,7 +992,7 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
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/* remove the TB from the hash list */
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phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
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h = tb_hash_func(phys_pc, tb->pc, tb->flags);
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tb_hash_remove(&tcg_ctx.tb_ctx.tb_phys_hash[h], tb);
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qht_remove(&tcg_ctx.tb_ctx.htable, tb, h);
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/* remove the TB from the page list */
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if (tb->page_addr[0] != page_addr) {
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@ -1128,13 +1122,10 @@ static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
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tb_page_addr_t phys_page2)
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{
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uint32_t h;
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TranslationBlock **ptb;
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/* add in the hash table */
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h = tb_hash_func(phys_pc, tb->pc, tb->flags);
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ptb = &tcg_ctx.tb_ctx.tb_phys_hash[h];
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tb->phys_hash_next = *ptb;
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*ptb = tb;
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qht_insert(&tcg_ctx.tb_ctx.htable, tb, h);
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/* add in the page list */
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tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK);
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