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ppc405_uc: convert to memory API

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Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Avi Kivity 2011-08-15 17:17:26 +03:00 committed by Anthony Liguori
parent c76f990e8d
commit 9074e0e3e8
1 changed files with 51 additions and 65 deletions
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116
hw/ppc405_uc.c
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@ -28,6 +28,7 @@
#include "qemu-timer.h" #include "qemu-timer.h"
#include "sysemu.h" #include "sysemu.h"
#include "qemu-log.h" #include "qemu-log.h"
#include "exec-memory.h"
#define DEBUG_OPBA #define DEBUG_OPBA
#define DEBUG_SDRAM #define DEBUG_SDRAM
@ -259,6 +260,7 @@ static void ppc4xx_pob_init(CPUState *env)
/* OPB arbitrer */ /* OPB arbitrer */
typedef struct ppc4xx_opba_t ppc4xx_opba_t; typedef struct ppc4xx_opba_t ppc4xx_opba_t;
struct ppc4xx_opba_t { struct ppc4xx_opba_t {
MemoryRegion io;
uint8_t cr; uint8_t cr;
uint8_t pr; uint8_t pr;
}; };
@ -357,16 +359,12 @@ static void opba_writel (void *opaque,
opba_writeb(opaque, addr + 1, value >> 16); opba_writeb(opaque, addr + 1, value >> 16);
} }
static CPUReadMemoryFunc * const opba_read[] = { static const MemoryRegionOps opba_ops = {
&opba_readb, .old_mmio = {
&opba_readw, .read = { opba_readb, opba_readw, opba_readl, },
&opba_readl, .write = { opba_writeb, opba_writew, opba_writel, },
}; },
.endianness = DEVICE_NATIVE_ENDIAN,
static CPUWriteMemoryFunc * const opba_write[] = {
&opba_writeb,
&opba_writew,
&opba_writel,
}; };
static void ppc4xx_opba_reset (void *opaque) static void ppc4xx_opba_reset (void *opaque)
@ -381,15 +379,13 @@ static void ppc4xx_opba_reset (void *opaque)
static void ppc4xx_opba_init(target_phys_addr_t base) static void ppc4xx_opba_init(target_phys_addr_t base)
{ {
ppc4xx_opba_t *opba; ppc4xx_opba_t *opba;
int io;
opba = g_malloc0(sizeof(ppc4xx_opba_t)); opba = g_malloc0(sizeof(ppc4xx_opba_t));
#ifdef DEBUG_OPBA #ifdef DEBUG_OPBA
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif #endif
io = cpu_register_io_memory(opba_read, opba_write, opba, memory_region_init_io(&opba->io, &opba_ops, opba, "opba", 0x002);
DEVICE_NATIVE_ENDIAN); memory_region_add_subregion(get_system_memory(), base, &opba->io);
cpu_register_physical_memory(base, 0x002, io);
qemu_register_reset(ppc4xx_opba_reset, opba); qemu_register_reset(ppc4xx_opba_reset, opba);
} }
@ -722,6 +718,7 @@ static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4])
/* GPIO */ /* GPIO */
typedef struct ppc405_gpio_t ppc405_gpio_t; typedef struct ppc405_gpio_t ppc405_gpio_t;
struct ppc405_gpio_t { struct ppc405_gpio_t {
MemoryRegion io;
uint32_t or; uint32_t or;
uint32_t tcr; uint32_t tcr;
uint32_t osrh; uint32_t osrh;
@ -789,16 +786,12 @@ static void ppc405_gpio_writel (void *opaque,
#endif #endif
} }
static CPUReadMemoryFunc * const ppc405_gpio_read[] = { static const MemoryRegionOps ppc405_gpio_ops = {
&ppc405_gpio_readb, .old_mmio = {
&ppc405_gpio_readw, .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, },
&ppc405_gpio_readl, .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, },
}; },
.endianness = DEVICE_NATIVE_ENDIAN,
static CPUWriteMemoryFunc * const ppc405_gpio_write[] = {
&ppc405_gpio_writeb,
&ppc405_gpio_writew,
&ppc405_gpio_writel,
}; };
static void ppc405_gpio_reset (void *opaque) static void ppc405_gpio_reset (void *opaque)
@ -808,15 +801,13 @@ static void ppc405_gpio_reset (void *opaque)
static void ppc405_gpio_init(target_phys_addr_t base) static void ppc405_gpio_init(target_phys_addr_t base)
{ {
ppc405_gpio_t *gpio; ppc405_gpio_t *gpio;
int io;
gpio = g_malloc0(sizeof(ppc405_gpio_t)); gpio = g_malloc0(sizeof(ppc405_gpio_t));
#ifdef DEBUG_GPIO #ifdef DEBUG_GPIO
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif #endif
io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio, memory_region_init_io(&gpio->io, &ppc405_gpio_ops, gpio, "pgio", 0x038);
DEVICE_NATIVE_ENDIAN); memory_region_add_subregion(get_system_memory(), base, &gpio->io);
cpu_register_physical_memory(base, 0x038, io);
qemu_register_reset(&ppc405_gpio_reset, gpio); qemu_register_reset(&ppc405_gpio_reset, gpio);
} }
@ -831,7 +822,9 @@ enum {
typedef struct ppc405_ocm_t ppc405_ocm_t; typedef struct ppc405_ocm_t ppc405_ocm_t;
struct ppc405_ocm_t { struct ppc405_ocm_t {
target_ulong offset; MemoryRegion ram;
MemoryRegion isarc_ram;
MemoryRegion dsarc_ram;
uint32_t isarc; uint32_t isarc;
uint32_t isacntl; uint32_t isacntl;
uint32_t dsarc; uint32_t dsarc;
@ -854,16 +847,15 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
if (ocm->isacntl & 0x80000000) { if (ocm->isacntl & 0x80000000) {
/* Unmap previously assigned memory region */ /* Unmap previously assigned memory region */
printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc); printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
cpu_register_physical_memory(ocm->isarc, 0x04000000, memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
IO_MEM_UNASSIGNED);
} }
if (isacntl & 0x80000000) { if (isacntl & 0x80000000) {
/* Map new instruction memory region */ /* Map new instruction memory region */
#ifdef DEBUG_OCM #ifdef DEBUG_OCM
printf("OCM map ISA %08" PRIx32 "\n", isarc); printf("OCM map ISA %08" PRIx32 "\n", isarc);
#endif #endif
cpu_register_physical_memory(isarc, 0x04000000, memory_region_add_subregion(get_system_memory(), isarc,
ocm->offset | IO_MEM_RAM); &ocm->isarc_ram);
} }
} }
if (ocm->dsarc != dsarc || if (ocm->dsarc != dsarc ||
@ -875,8 +867,8 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
#ifdef DEBUG_OCM #ifdef DEBUG_OCM
printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc); printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
#endif #endif
cpu_register_physical_memory(ocm->dsarc, 0x04000000, memory_region_del_subregion(get_system_memory(),
IO_MEM_UNASSIGNED); &ocm->dsarc_ram);
} }
} }
if (dsacntl & 0x80000000) { if (dsacntl & 0x80000000) {
@ -886,8 +878,8 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
#ifdef DEBUG_OCM #ifdef DEBUG_OCM
printf("OCM map DSA %08" PRIx32 "\n", dsarc); printf("OCM map DSA %08" PRIx32 "\n", dsarc);
#endif #endif
cpu_register_physical_memory(dsarc, 0x04000000, memory_region_add_subregion(get_system_memory(), dsarc,
ocm->offset | IO_MEM_RAM); &ocm->dsarc_ram);
} }
} }
} }
@ -973,7 +965,10 @@ static void ppc405_ocm_init(CPUState *env)
ppc405_ocm_t *ocm; ppc405_ocm_t *ocm;
ocm = g_malloc0(sizeof(ppc405_ocm_t)); ocm = g_malloc0(sizeof(ppc405_ocm_t));
ocm->offset = qemu_ram_alloc(NULL, "ppc405.ocm", 4096); /* XXX: Size is 4096 or 0x04000000 */
memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096);
memory_region_init_alias(&ocm->dsarc_ram, "ppc405.dsarc", &ocm->isarc_ram,
0, 4096);
qemu_register_reset(&ocm_reset, ocm); qemu_register_reset(&ocm_reset, ocm);
ppc_dcr_register(env, OCM0_ISARC, ppc_dcr_register(env, OCM0_ISARC,
ocm, &dcr_read_ocm, &dcr_write_ocm); ocm, &dcr_read_ocm, &dcr_write_ocm);
@ -990,6 +985,7 @@ static void ppc405_ocm_init(CPUState *env)
typedef struct ppc4xx_i2c_t ppc4xx_i2c_t; typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
struct ppc4xx_i2c_t { struct ppc4xx_i2c_t {
qemu_irq irq; qemu_irq irq;
MemoryRegion iomem;
uint8_t mdata; uint8_t mdata;
uint8_t lmadr; uint8_t lmadr;
uint8_t hmadr; uint8_t hmadr;
@ -1186,16 +1182,12 @@ static void ppc4xx_i2c_writel (void *opaque,
ppc4xx_i2c_writeb(opaque, addr + 3, value); ppc4xx_i2c_writeb(opaque, addr + 3, value);
} }
static CPUReadMemoryFunc * const i2c_read[] = { static const MemoryRegionOps i2c_ops = {
&ppc4xx_i2c_readb, .old_mmio = {
&ppc4xx_i2c_readw, .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },
&ppc4xx_i2c_readl, .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },
}; },
.endianness = DEVICE_NATIVE_ENDIAN,
static CPUWriteMemoryFunc * const i2c_write[] = {
&ppc4xx_i2c_writeb,
&ppc4xx_i2c_writew,
&ppc4xx_i2c_writel,
}; };
static void ppc4xx_i2c_reset (void *opaque) static void ppc4xx_i2c_reset (void *opaque)
@ -1217,16 +1209,14 @@ static void ppc4xx_i2c_reset (void *opaque)
static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq) static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
{ {
ppc4xx_i2c_t *i2c; ppc4xx_i2c_t *i2c;
int io;
i2c = g_malloc0(sizeof(ppc4xx_i2c_t)); i2c = g_malloc0(sizeof(ppc4xx_i2c_t));
i2c->irq = irq; i2c->irq = irq;
#ifdef DEBUG_I2C #ifdef DEBUG_I2C
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif #endif
io = cpu_register_io_memory(i2c_read, i2c_write, i2c, memory_region_init_io(&i2c->iomem, &i2c_ops, i2c, "i2c", 0x011);
DEVICE_NATIVE_ENDIAN); memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);
cpu_register_physical_memory(base, 0x011, io);
qemu_register_reset(ppc4xx_i2c_reset, i2c); qemu_register_reset(ppc4xx_i2c_reset, i2c);
} }
@ -1234,6 +1224,7 @@ static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
/* General purpose timers */ /* General purpose timers */
typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
struct ppc4xx_gpt_t { struct ppc4xx_gpt_t {
MemoryRegion iomem;
int64_t tb_offset; int64_t tb_offset;
uint32_t tb_freq; uint32_t tb_freq;
struct QEMUTimer *timer; struct QEMUTimer *timer;
@ -1454,16 +1445,12 @@ static void ppc4xx_gpt_writel (void *opaque,
} }
} }
static CPUReadMemoryFunc * const gpt_read[] = { static const MemoryRegionOps gpt_ops = {
&ppc4xx_gpt_readb, .old_mmio = {
&ppc4xx_gpt_readw, .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, },
&ppc4xx_gpt_readl, .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, },
}; },
.endianness = DEVICE_NATIVE_ENDIAN,
static CPUWriteMemoryFunc * const gpt_write[] = {
&ppc4xx_gpt_writeb,
&ppc4xx_gpt_writew,
&ppc4xx_gpt_writel,
}; };
static void ppc4xx_gpt_cb (void *opaque) static void ppc4xx_gpt_cb (void *opaque)
@ -1498,7 +1485,6 @@ static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
{ {
ppc4xx_gpt_t *gpt; ppc4xx_gpt_t *gpt;
int i; int i;
int io;
gpt = g_malloc0(sizeof(ppc4xx_gpt_t)); gpt = g_malloc0(sizeof(ppc4xx_gpt_t));
for (i = 0; i < 5; i++) { for (i = 0; i < 5; i++) {
@ -1508,8 +1494,8 @@ static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
#ifdef DEBUG_GPT #ifdef DEBUG_GPT
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif #endif
io = cpu_register_io_memory(gpt_read, gpt_write, gpt, DEVICE_NATIVE_ENDIAN); memory_region_init_io(&gpt->iomem, &gpt_ops, gpt, "gpt", 0x0d4);
cpu_register_physical_memory(base, 0x0d4, io); memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
qemu_register_reset(ppc4xx_gpt_reset, gpt); qemu_register_reset(ppc4xx_gpt_reset, gpt);
} }