ppc405_uc: convert to memory API
Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Avi Kivity
Anthony Liguori
parent
c76f990e8d
commit
9074e0e3e8
116
hw/ppc405_uc.c
116
hw/ppc405_uc.c
@ -28,6 +28,7 @@
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#include "qemu-timer.h"
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#include "sysemu.h"
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#include "qemu-log.h"
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#include "exec-memory.h"
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#define DEBUG_OPBA
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#define DEBUG_SDRAM
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@ -259,6 +260,7 @@ static void ppc4xx_pob_init(CPUState *env)
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/* OPB arbitrer */
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typedef struct ppc4xx_opba_t ppc4xx_opba_t;
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struct ppc4xx_opba_t {
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MemoryRegion io;
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uint8_t cr;
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uint8_t pr;
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};
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@ -357,16 +359,12 @@ static void opba_writel (void *opaque,
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opba_writeb(opaque, addr + 1, value >> 16);
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}
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static CPUReadMemoryFunc * const opba_read[] = {
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&opba_readb,
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&opba_readw,
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&opba_readl,
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};
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static CPUWriteMemoryFunc * const opba_write[] = {
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&opba_writeb,
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&opba_writew,
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&opba_writel,
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static const MemoryRegionOps opba_ops = {
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.old_mmio = {
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.read = { opba_readb, opba_readw, opba_readl, },
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.write = { opba_writeb, opba_writew, opba_writel, },
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void ppc4xx_opba_reset (void *opaque)
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@ -381,15 +379,13 @@ static void ppc4xx_opba_reset (void *opaque)
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static void ppc4xx_opba_init(target_phys_addr_t base)
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{
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ppc4xx_opba_t *opba;
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int io;
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opba = g_malloc0(sizeof(ppc4xx_opba_t));
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#ifdef DEBUG_OPBA
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printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
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#endif
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io = cpu_register_io_memory(opba_read, opba_write, opba,
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DEVICE_NATIVE_ENDIAN);
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cpu_register_physical_memory(base, 0x002, io);
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memory_region_init_io(&opba->io, &opba_ops, opba, "opba", 0x002);
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memory_region_add_subregion(get_system_memory(), base, &opba->io);
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qemu_register_reset(ppc4xx_opba_reset, opba);
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}
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@ -722,6 +718,7 @@ static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4])
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/* GPIO */
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typedef struct ppc405_gpio_t ppc405_gpio_t;
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struct ppc405_gpio_t {
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MemoryRegion io;
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uint32_t or;
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uint32_t tcr;
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uint32_t osrh;
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@ -789,16 +786,12 @@ static void ppc405_gpio_writel (void *opaque,
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#endif
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}
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static CPUReadMemoryFunc * const ppc405_gpio_read[] = {
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&ppc405_gpio_readb,
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&ppc405_gpio_readw,
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&ppc405_gpio_readl,
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};
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static CPUWriteMemoryFunc * const ppc405_gpio_write[] = {
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&ppc405_gpio_writeb,
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&ppc405_gpio_writew,
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&ppc405_gpio_writel,
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static const MemoryRegionOps ppc405_gpio_ops = {
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.old_mmio = {
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.read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, },
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.write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, },
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void ppc405_gpio_reset (void *opaque)
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@ -808,15 +801,13 @@ static void ppc405_gpio_reset (void *opaque)
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static void ppc405_gpio_init(target_phys_addr_t base)
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{
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ppc405_gpio_t *gpio;
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int io;
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gpio = g_malloc0(sizeof(ppc405_gpio_t));
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#ifdef DEBUG_GPIO
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printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
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#endif
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io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio,
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DEVICE_NATIVE_ENDIAN);
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cpu_register_physical_memory(base, 0x038, io);
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memory_region_init_io(&gpio->io, &ppc405_gpio_ops, gpio, "pgio", 0x038);
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memory_region_add_subregion(get_system_memory(), base, &gpio->io);
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qemu_register_reset(&ppc405_gpio_reset, gpio);
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}
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@ -831,7 +822,9 @@ enum {
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typedef struct ppc405_ocm_t ppc405_ocm_t;
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struct ppc405_ocm_t {
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target_ulong offset;
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MemoryRegion ram;
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MemoryRegion isarc_ram;
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MemoryRegion dsarc_ram;
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uint32_t isarc;
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uint32_t isacntl;
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uint32_t dsarc;
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@ -854,16 +847,15 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
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if (ocm->isacntl & 0x80000000) {
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/* Unmap previously assigned memory region */
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printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
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cpu_register_physical_memory(ocm->isarc, 0x04000000,
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IO_MEM_UNASSIGNED);
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memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
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}
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if (isacntl & 0x80000000) {
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/* Map new instruction memory region */
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#ifdef DEBUG_OCM
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printf("OCM map ISA %08" PRIx32 "\n", isarc);
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#endif
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cpu_register_physical_memory(isarc, 0x04000000,
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ocm->offset | IO_MEM_RAM);
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memory_region_add_subregion(get_system_memory(), isarc,
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&ocm->isarc_ram);
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}
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}
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if (ocm->dsarc != dsarc ||
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@ -875,8 +867,8 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
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#ifdef DEBUG_OCM
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printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
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#endif
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cpu_register_physical_memory(ocm->dsarc, 0x04000000,
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IO_MEM_UNASSIGNED);
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memory_region_del_subregion(get_system_memory(),
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&ocm->dsarc_ram);
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}
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}
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if (dsacntl & 0x80000000) {
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@ -886,8 +878,8 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
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#ifdef DEBUG_OCM
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printf("OCM map DSA %08" PRIx32 "\n", dsarc);
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#endif
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cpu_register_physical_memory(dsarc, 0x04000000,
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ocm->offset | IO_MEM_RAM);
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memory_region_add_subregion(get_system_memory(), dsarc,
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&ocm->dsarc_ram);
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}
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}
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}
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@ -973,7 +965,10 @@ static void ppc405_ocm_init(CPUState *env)
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ppc405_ocm_t *ocm;
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ocm = g_malloc0(sizeof(ppc405_ocm_t));
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ocm->offset = qemu_ram_alloc(NULL, "ppc405.ocm", 4096);
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/* XXX: Size is 4096 or 0x04000000 */
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memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096);
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memory_region_init_alias(&ocm->dsarc_ram, "ppc405.dsarc", &ocm->isarc_ram,
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0, 4096);
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qemu_register_reset(&ocm_reset, ocm);
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ppc_dcr_register(env, OCM0_ISARC,
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ocm, &dcr_read_ocm, &dcr_write_ocm);
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@ -990,6 +985,7 @@ static void ppc405_ocm_init(CPUState *env)
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typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
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struct ppc4xx_i2c_t {
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qemu_irq irq;
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MemoryRegion iomem;
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uint8_t mdata;
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uint8_t lmadr;
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uint8_t hmadr;
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@ -1186,16 +1182,12 @@ static void ppc4xx_i2c_writel (void *opaque,
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ppc4xx_i2c_writeb(opaque, addr + 3, value);
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}
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static CPUReadMemoryFunc * const i2c_read[] = {
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&ppc4xx_i2c_readb,
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&ppc4xx_i2c_readw,
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&ppc4xx_i2c_readl,
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};
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static CPUWriteMemoryFunc * const i2c_write[] = {
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&ppc4xx_i2c_writeb,
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&ppc4xx_i2c_writew,
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&ppc4xx_i2c_writel,
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static const MemoryRegionOps i2c_ops = {
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.old_mmio = {
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.read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },
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.write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void ppc4xx_i2c_reset (void *opaque)
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@ -1217,16 +1209,14 @@ static void ppc4xx_i2c_reset (void *opaque)
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static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
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{
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ppc4xx_i2c_t *i2c;
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int io;
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i2c = g_malloc0(sizeof(ppc4xx_i2c_t));
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i2c->irq = irq;
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#ifdef DEBUG_I2C
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printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
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#endif
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io = cpu_register_io_memory(i2c_read, i2c_write, i2c,
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DEVICE_NATIVE_ENDIAN);
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cpu_register_physical_memory(base, 0x011, io);
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memory_region_init_io(&i2c->iomem, &i2c_ops, i2c, "i2c", 0x011);
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memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);
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qemu_register_reset(ppc4xx_i2c_reset, i2c);
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}
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@ -1234,6 +1224,7 @@ static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
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/* General purpose timers */
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typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
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struct ppc4xx_gpt_t {
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MemoryRegion iomem;
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int64_t tb_offset;
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uint32_t tb_freq;
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struct QEMUTimer *timer;
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@ -1454,16 +1445,12 @@ static void ppc4xx_gpt_writel (void *opaque,
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}
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}
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static CPUReadMemoryFunc * const gpt_read[] = {
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&ppc4xx_gpt_readb,
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&ppc4xx_gpt_readw,
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&ppc4xx_gpt_readl,
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};
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static CPUWriteMemoryFunc * const gpt_write[] = {
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&ppc4xx_gpt_writeb,
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&ppc4xx_gpt_writew,
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&ppc4xx_gpt_writel,
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static const MemoryRegionOps gpt_ops = {
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.old_mmio = {
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.read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, },
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.write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, },
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void ppc4xx_gpt_cb (void *opaque)
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@ -1498,7 +1485,6 @@ static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
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{
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ppc4xx_gpt_t *gpt;
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int i;
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int io;
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gpt = g_malloc0(sizeof(ppc4xx_gpt_t));
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for (i = 0; i < 5; i++) {
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@ -1508,8 +1494,8 @@ static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
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#ifdef DEBUG_GPT
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printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
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#endif
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io = cpu_register_io_memory(gpt_read, gpt_write, gpt, DEVICE_NATIVE_ENDIAN);
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cpu_register_physical_memory(base, 0x0d4, io);
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memory_region_init_io(&gpt->iomem, &gpt_ops, gpt, "gpt", 0x0d4);
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memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
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qemu_register_reset(ppc4xx_gpt_reset, gpt);
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}
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