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target/ppc: Add HASHKEYR and HASHPKEYR SPRs

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Add the Special Purpose Registers HASHKEYR and HASHPKEYR, which were
introduced by the Power ISA 3.1B. They are used by the new instructions
hashchk(p) and hashst(p).

The ISA states that the Operating System should generate the value for
these registers when creating a process, so it's its responsability to
do so. We initialize it with 0 for qemu-softmmu, and set a random 64
bits value for linux-user.

Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br>
Message-Id: <20220715205439.161110-2-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Víctor Colombo 2022-07-15 17:54:37 -03:00 committed by Daniel Henrique Barboza
parent d29201ff34
commit 903f84eb88
2 changed files with 30 additions and 0 deletions
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2
target/ppc/cpu.h
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@ -1676,6 +1676,8 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_BOOKE_GIVOR14 (0x1BD)
#define SPR_TIR (0x1BE)
#define SPR_PTCR (0x1D0)
#define SPR_HASHKEYR (0x1D4)
#define SPR_HASHPKEYR (0x1D5)
#define SPR_BOOKE_SPEFSCR (0x200)
#define SPR_Exxx_BBEAR (0x201)
#define SPR_Exxx_BBTAR (0x202)

28
target/ppc/cpu_init.c
View File

@ -5700,6 +5700,33 @@ static void register_power9_mmu_sprs(CPUPPCState *env)
#endif
}
static void register_power10_hash_sprs(CPUPPCState *env)
{
/*
* it's the OS responsability to generate a random value for the registers
* in each process' context. So, initialize it with 0 here.
*/
uint64_t hashkeyr_initial_value = 0, hashpkeyr_initial_value = 0;
#if defined(CONFIG_USER_ONLY)
/* in linux-user, setup the hash register with a random value */
GRand *rand = g_rand_new();
hashkeyr_initial_value =
((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand);
hashpkeyr_initial_value =
((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand);
g_rand_free(rand);
#endif
spr_register(env, SPR_HASHKEYR, "HASHKEYR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
hashkeyr_initial_value);
spr_register_hv(env, SPR_HASHPKEYR, "HASHPKEYR",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
hashpkeyr_initial_value);
}
/*
* Initialize PMU counter overflow timers for Power8 and
* newer Power chips when using TCG.
@ -6518,6 +6545,7 @@ static void init_proc_POWER10(CPUPPCState *env)
register_power8_book4_sprs(env);
register_power8_rpr_sprs(env);
register_power9_mmu_sprs(env);
register_power10_hash_sprs(env);
/* FIXME: Filter fields properly based on privilege level */
spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,