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target-arm: Recognize ROR

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-id: 1441909103-24666-11-git-send-email-rth@twiddle.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2015-09-14 14:39:49 +01:00 committed by Peter Maydell
parent d3a77b42de
commit 8fb0ad8e16
1 changed files with 21 additions and 12 deletions
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33
target-arm/translate-a64.c
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@ -3117,17 +3117,7 @@ static void disas_extract(DisasContext *s, uint32_t insn)
tcg_rd = cpu_reg(s, rd); tcg_rd = cpu_reg(s, rd);
if (imm) { if (unlikely(imm == 0)) {
/* OPTME: we can special case rm==rn as a rotate */
tcg_rm = read_cpu_reg(s, rm, sf);
tcg_rn = read_cpu_reg(s, rn, sf);
tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
if (!sf) {
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
}
} else {
/* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts, /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
* so an extract from bit 0 is a special case. * so an extract from bit 0 is a special case.
*/ */
@ -3136,8 +3126,27 @@ static void disas_extract(DisasContext *s, uint32_t insn)
} else { } else {
tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm)); tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
} }
} else if (rm == rn) { /* ROR */
tcg_rm = cpu_reg(s, rm);
if (sf) {
tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm);
} else {
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(tmp, tcg_rm);
tcg_gen_rotri_i32(tmp, tmp, imm);
tcg_gen_extu_i32_i64(tcg_rd, tmp);
tcg_temp_free_i32(tmp);
}
} else {
tcg_rm = read_cpu_reg(s, rm, sf);
tcg_rn = read_cpu_reg(s, rn, sf);
tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
if (!sf) {
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
}
} }
} }
} }