accel/tcg: Remove cpu_set_cpustate_pointers
This function is now empty, so remove it. In the case of m68k and tricore, this empties the class instance initfn, so remove those as well. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
parent
b77af26e97
commit
8fa08d7ec7
@ -423,16 +423,6 @@ void dump_exec_info(GString *buf);
|
|||||||
/* accel/tcg/cpu-exec.c */
|
/* accel/tcg/cpu-exec.c */
|
||||||
int cpu_exec(CPUState *cpu);
|
int cpu_exec(CPUState *cpu);
|
||||||
|
|
||||||
/**
|
|
||||||
* cpu_set_cpustate_pointers(cpu)
|
|
||||||
* @cpu: The cpu object
|
|
||||||
*
|
|
||||||
* Set the generic pointers in CPUState into the outer object.
|
|
||||||
*/
|
|
||||||
static inline void cpu_set_cpustate_pointers(ArchCPU *cpu)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Validate correct placement of CPUArchState. */
|
/* Validate correct placement of CPUArchState. */
|
||||||
QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0);
|
QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0);
|
||||||
QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState));
|
QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState));
|
||||||
|
@ -209,8 +209,6 @@ static void alpha_cpu_initfn(Object *obj)
|
|||||||
AlphaCPU *cpu = ALPHA_CPU(obj);
|
AlphaCPU *cpu = ALPHA_CPU(obj);
|
||||||
CPUAlphaState *env = &cpu->env;
|
CPUAlphaState *env = &cpu->env;
|
||||||
|
|
||||||
cpu_set_cpustate_pointers(cpu);
|
|
||||||
|
|
||||||
env->lock_addr = -1;
|
env->lock_addr = -1;
|
||||||
#if defined(CONFIG_USER_ONLY)
|
#if defined(CONFIG_USER_ONLY)
|
||||||
env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;
|
env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;
|
||||||
|
@ -1215,7 +1215,6 @@ static void arm_cpu_initfn(Object *obj)
|
|||||||
{
|
{
|
||||||
ARMCPU *cpu = ARM_CPU(obj);
|
ARMCPU *cpu = ARM_CPU(obj);
|
||||||
|
|
||||||
cpu_set_cpustate_pointers(cpu);
|
|
||||||
cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal,
|
cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal,
|
||||||
NULL, g_free);
|
NULL, g_free);
|
||||||
|
|
||||||
|
@ -147,8 +147,6 @@ static void avr_cpu_initfn(Object *obj)
|
|||||||
{
|
{
|
||||||
AVRCPU *cpu = AVR_CPU(obj);
|
AVRCPU *cpu = AVR_CPU(obj);
|
||||||
|
|
||||||
cpu_set_cpustate_pointers(cpu);
|
|
||||||
|
|
||||||
/* Set the number of interrupts supported by the CPU. */
|
/* Set the number of interrupts supported by the CPU. */
|
||||||
qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int,
|
qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int,
|
||||||
sizeof(cpu->env.intsrc) * 8);
|
sizeof(cpu->env.intsrc) * 8);
|
||||||
|
@ -201,8 +201,6 @@ static void cris_cpu_initfn(Object *obj)
|
|||||||
CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
|
CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
|
||||||
CPUCRISState *env = &cpu->env;
|
CPUCRISState *env = &cpu->env;
|
||||||
|
|
||||||
cpu_set_cpustate_pointers(cpu);
|
|
||||||
|
|
||||||
env->pregs[PR_VR] = ccc->vr;
|
env->pregs[PR_VR] = ccc->vr;
|
||||||
|
|
||||||
#ifndef CONFIG_USER_ONLY
|
#ifndef CONFIG_USER_ONLY
|
||||||
|
@ -353,9 +353,6 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp)
|
|||||||
|
|
||||||
static void hexagon_cpu_init(Object *obj)
|
static void hexagon_cpu_init(Object *obj)
|
||||||
{
|
{
|
||||||
HexagonCPU *cpu = HEXAGON_CPU(obj);
|
|
||||||
|
|
||||||
cpu_set_cpustate_pointers(cpu);
|
|
||||||
qdev_property_add_static(DEVICE(obj), &hexagon_lldb_compat_property);
|
qdev_property_add_static(DEVICE(obj), &hexagon_lldb_compat_property);
|
||||||
qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property);
|
qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property);
|
||||||
qdev_property_add_static(DEVICE(obj), &hexagon_short_circuit_property);
|
qdev_property_add_static(DEVICE(obj), &hexagon_short_circuit_property);
|
||||||
|
@ -149,7 +149,6 @@ static void hppa_cpu_initfn(Object *obj)
|
|||||||
HPPACPU *cpu = HPPA_CPU(obj);
|
HPPACPU *cpu = HPPA_CPU(obj);
|
||||||
CPUHPPAState *env = &cpu->env;
|
CPUHPPAState *env = &cpu->env;
|
||||||
|
|
||||||
cpu_set_cpustate_pointers(cpu);
|
|
||||||
cs->exception_index = -1;
|
cs->exception_index = -1;
|
||||||
cpu_hppa_loaded_fr0(env);
|
cpu_hppa_loaded_fr0(env);
|
||||||
cpu_hppa_put_psw(env, PSW_W);
|
cpu_hppa_put_psw(env, PSW_W);
|
||||||
|
@ -7590,7 +7590,6 @@ static void x86_cpu_initfn(Object *obj)
|
|||||||
CPUX86State *env = &cpu->env;
|
CPUX86State *env = &cpu->env;
|
||||||
|
|
||||||
env->nr_dies = 1;
|
env->nr_dies = 1;
|
||||||
cpu_set_cpustate_pointers(cpu);
|
|
||||||
|
|
||||||
object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
|
object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
|
||||||
x86_cpu_get_feature_words,
|
x86_cpu_get_feature_words,
|
||||||
|
@ -618,17 +618,15 @@ static const MemoryRegionOps loongarch_qemu_ops = {
|
|||||||
|
|
||||||
static void loongarch_cpu_init(Object *obj)
|
static void loongarch_cpu_init(Object *obj)
|
||||||
{
|
{
|
||||||
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
|
|
||||||
|
|
||||||
cpu_set_cpustate_pointers(cpu);
|
|
||||||
|
|
||||||
#ifndef CONFIG_USER_ONLY
|
#ifndef CONFIG_USER_ONLY
|
||||||
|
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
|
||||||
CPULoongArchState *env = &cpu->env;
|
CPULoongArchState *env = &cpu->env;
|
||||||
|
|
||||||
qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS);
|
qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS);
|
||||||
timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL,
|
timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL,
|
||||||
&loongarch_constant_timer_cb, cpu);
|
&loongarch_constant_timer_cb, cpu);
|
||||||
memory_region_init_io(&env->system_iocsr, OBJECT(cpu), NULL,
|
memory_region_init_io(&env->system_iocsr, OBJECT(cpu), NULL,
|
||||||
env, "iocsr", UINT64_MAX);
|
env, "iocsr", UINT64_MAX);
|
||||||
address_space_init(&env->address_space_iocsr, &env->system_iocsr, "IOCSR");
|
address_space_init(&env->address_space_iocsr, &env->system_iocsr, "IOCSR");
|
||||||
memory_region_init_io(&env->iocsr_mem, OBJECT(cpu), &loongarch_qemu_ops,
|
memory_region_init_io(&env->iocsr_mem, OBJECT(cpu), &loongarch_qemu_ops,
|
||||||
NULL, "iocsr_misc", 0x428);
|
NULL, "iocsr_misc", 0x428);
|
||||||
|
@ -327,13 +327,6 @@ static void m68k_cpu_realizefn(DeviceState *dev, Error **errp)
|
|||||||
mcc->parent_realize(dev, errp);
|
mcc->parent_realize(dev, errp);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void m68k_cpu_initfn(Object *obj)
|
|
||||||
{
|
|
||||||
M68kCPU *cpu = M68K_CPU(obj);
|
|
||||||
|
|
||||||
cpu_set_cpustate_pointers(cpu);
|
|
||||||
}
|
|
||||||
|
|
||||||
#if !defined(CONFIG_USER_ONLY)
|
#if !defined(CONFIG_USER_ONLY)
|
||||||
static bool fpu_needed(void *opaque)
|
static bool fpu_needed(void *opaque)
|
||||||
{
|
{
|
||||||
@ -612,7 +605,6 @@ static const TypeInfo m68k_cpus_type_infos[] = {
|
|||||||
.parent = TYPE_CPU,
|
.parent = TYPE_CPU,
|
||||||
.instance_size = sizeof(M68kCPU),
|
.instance_size = sizeof(M68kCPU),
|
||||||
.instance_align = __alignof(M68kCPU),
|
.instance_align = __alignof(M68kCPU),
|
||||||
.instance_init = m68k_cpu_initfn,
|
|
||||||
.abstract = true,
|
.abstract = true,
|
||||||
.class_size = sizeof(M68kCPUClass),
|
.class_size = sizeof(M68kCPUClass),
|
||||||
.class_init = m68k_cpu_class_init,
|
.class_init = m68k_cpu_class_init,
|
||||||
|
@ -296,7 +296,6 @@ static void mb_cpu_initfn(Object *obj)
|
|||||||
MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
|
MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
|
||||||
CPUMBState *env = &cpu->env;
|
CPUMBState *env = &cpu->env;
|
||||||
|
|
||||||
cpu_set_cpustate_pointers(cpu);
|
|
||||||
gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect,
|
gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect,
|
||||||
mb_cpu_gdb_write_stack_protect, 2,
|
mb_cpu_gdb_write_stack_protect, 2,
|
||||||
"microblaze-stack-protect.xml", 0);
|
"microblaze-stack-protect.xml", 0);
|
||||||
|
@ -504,7 +504,6 @@ static void mips_cpu_initfn(Object *obj)
|
|||||||
CPUMIPSState *env = &cpu->env;
|
CPUMIPSState *env = &cpu->env;
|
||||||
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);
|
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);
|
||||||
|
|
||||||
cpu_set_cpustate_pointers(cpu);
|
|
||||||
cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0);
|
cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0);
|
||||||
cpu->count_div = clock_new(OBJECT(obj), "clk-div-count");
|
cpu->count_div = clock_new(OBJECT(obj), "clk-div-count");
|
||||||
env->count_clock = clock_new(OBJECT(obj), "clk-count");
|
env->count_clock = clock_new(OBJECT(obj), "clk-count");
|
||||||
|
@ -113,11 +113,9 @@ static void iic_set_irq(void *opaque, int irq, int level)
|
|||||||
|
|
||||||
static void nios2_cpu_initfn(Object *obj)
|
static void nios2_cpu_initfn(Object *obj)
|
||||||
{
|
{
|
||||||
|
#if !defined(CONFIG_USER_ONLY)
|
||||||
Nios2CPU *cpu = NIOS2_CPU(obj);
|
Nios2CPU *cpu = NIOS2_CPU(obj);
|
||||||
|
|
||||||
cpu_set_cpustate_pointers(cpu);
|
|
||||||
|
|
||||||
#if !defined(CONFIG_USER_ONLY)
|
|
||||||
mmu_init(&cpu->env);
|
mmu_init(&cpu->env);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
@ -149,12 +149,8 @@ static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
|
|||||||
|
|
||||||
static void openrisc_cpu_initfn(Object *obj)
|
static void openrisc_cpu_initfn(Object *obj)
|
||||||
{
|
{
|
||||||
OpenRISCCPU *cpu = OPENRISC_CPU(obj);
|
|
||||||
|
|
||||||
cpu_set_cpustate_pointers(cpu);
|
|
||||||
|
|
||||||
#ifndef CONFIG_USER_ONLY
|
#ifndef CONFIG_USER_ONLY
|
||||||
qdev_init_gpio_in_named(DEVICE(cpu), openrisc_cpu_set_irq, "IRQ", NR_IRQS);
|
qdev_init_gpio_in_named(DEVICE(obj), openrisc_cpu_set_irq, "IRQ", NR_IRQS);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -7246,7 +7246,6 @@ static void ppc_cpu_instance_init(Object *obj)
|
|||||||
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
|
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
|
||||||
CPUPPCState *env = &cpu->env;
|
CPUPPCState *env = &cpu->env;
|
||||||
|
|
||||||
cpu_set_cpustate_pointers(cpu);
|
|
||||||
cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
|
cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
|
||||||
|
|
||||||
env->msr_mask = pcc->msr_mask;
|
env->msr_mask = pcc->msr_mask;
|
||||||
|
@ -1649,12 +1649,8 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
|
|||||||
|
|
||||||
static void riscv_cpu_init(Object *obj)
|
static void riscv_cpu_init(Object *obj)
|
||||||
{
|
{
|
||||||
RISCVCPU *cpu = RISCV_CPU(obj);
|
|
||||||
|
|
||||||
cpu_set_cpustate_pointers(cpu);
|
|
||||||
|
|
||||||
#ifndef CONFIG_USER_ONLY
|
#ifndef CONFIG_USER_ONLY
|
||||||
qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
|
qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
|
||||||
IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
|
IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
|
||||||
#endif /* CONFIG_USER_ONLY */
|
#endif /* CONFIG_USER_ONLY */
|
||||||
}
|
}
|
||||||
|
@ -185,7 +185,6 @@ static void rx_cpu_init(Object *obj)
|
|||||||
{
|
{
|
||||||
RXCPU *cpu = RX_CPU(obj);
|
RXCPU *cpu = RX_CPU(obj);
|
||||||
|
|
||||||
cpu_set_cpustate_pointers(cpu);
|
|
||||||
qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
|
qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -274,9 +274,7 @@ out:
|
|||||||
static void s390_cpu_initfn(Object *obj)
|
static void s390_cpu_initfn(Object *obj)
|
||||||
{
|
{
|
||||||
CPUState *cs = CPU(obj);
|
CPUState *cs = CPU(obj);
|
||||||
S390CPU *cpu = S390_CPU(obj);
|
|
||||||
|
|
||||||
cpu_set_cpustate_pointers(cpu);
|
|
||||||
cs->exception_index = EXCP_HLT;
|
cs->exception_index = EXCP_HLT;
|
||||||
|
|
||||||
#if !defined(CONFIG_USER_ONLY)
|
#if !defined(CONFIG_USER_ONLY)
|
||||||
|
@ -239,8 +239,6 @@ static void superh_cpu_initfn(Object *obj)
|
|||||||
SuperHCPU *cpu = SUPERH_CPU(obj);
|
SuperHCPU *cpu = SUPERH_CPU(obj);
|
||||||
CPUSH4State *env = &cpu->env;
|
CPUSH4State *env = &cpu->env;
|
||||||
|
|
||||||
cpu_set_cpustate_pointers(cpu);
|
|
||||||
|
|
||||||
env->movcal_backup_tail = &(env->movcal_backup);
|
env->movcal_backup_tail = &(env->movcal_backup);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -793,8 +793,6 @@ static void sparc_cpu_initfn(Object *obj)
|
|||||||
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
|
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
|
||||||
CPUSPARCState *env = &cpu->env;
|
CPUSPARCState *env = &cpu->env;
|
||||||
|
|
||||||
cpu_set_cpustate_pointers(cpu);
|
|
||||||
|
|
||||||
if (scc->cpu_def) {
|
if (scc->cpu_def) {
|
||||||
env->def = *scc->cpu_def;
|
env->def = *scc->cpu_def;
|
||||||
}
|
}
|
||||||
|
@ -124,14 +124,6 @@ static void tricore_cpu_realizefn(DeviceState *dev, Error **errp)
|
|||||||
tcc->parent_realize(dev, errp);
|
tcc->parent_realize(dev, errp);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
static void tricore_cpu_initfn(Object *obj)
|
|
||||||
{
|
|
||||||
TriCoreCPU *cpu = TRICORE_CPU(obj);
|
|
||||||
|
|
||||||
cpu_set_cpustate_pointers(cpu);
|
|
||||||
}
|
|
||||||
|
|
||||||
static ObjectClass *tricore_cpu_class_by_name(const char *cpu_model)
|
static ObjectClass *tricore_cpu_class_by_name(const char *cpu_model)
|
||||||
{
|
{
|
||||||
ObjectClass *oc;
|
ObjectClass *oc;
|
||||||
@ -231,7 +223,6 @@ static const TypeInfo tricore_cpu_type_infos[] = {
|
|||||||
.parent = TYPE_CPU,
|
.parent = TYPE_CPU,
|
||||||
.instance_size = sizeof(TriCoreCPU),
|
.instance_size = sizeof(TriCoreCPU),
|
||||||
.instance_align = __alignof(TriCoreCPU),
|
.instance_align = __alignof(TriCoreCPU),
|
||||||
.instance_init = tricore_cpu_initfn,
|
|
||||||
.abstract = true,
|
.abstract = true,
|
||||||
.class_size = sizeof(TriCoreCPUClass),
|
.class_size = sizeof(TriCoreCPUClass),
|
||||||
.class_init = tricore_cpu_class_init,
|
.class_init = tricore_cpu_class_init,
|
||||||
|
@ -185,7 +185,6 @@ static void xtensa_cpu_initfn(Object *obj)
|
|||||||
XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
|
XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
|
||||||
CPUXtensaState *env = &cpu->env;
|
CPUXtensaState *env = &cpu->env;
|
||||||
|
|
||||||
cpu_set_cpustate_pointers(cpu);
|
|
||||||
env->config = xcc->config;
|
env->config = xcc->config;
|
||||||
|
|
||||||
#ifndef CONFIG_USER_ONLY
|
#ifndef CONFIG_USER_ONLY
|
||||||
|
Loading…
Reference in New Issue
Block a user