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hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions

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This was done in the virt & sifive_u codes, but sifive_e codes were
missed. Remove the riscv_ prefix of the machine* and soc* functions.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-2-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Bin Meng 2020-06-08 07:17:30 -07:00 committed by Alistair Francis
parent 1145188e09
commit 8f8c6c1a64
1 changed files with 12 additions and 12 deletions
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24
hw/riscv/sifive_e.c
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@ -75,7 +75,7 @@ static const struct MemmapEntry {
[SIFIVE_E_DTIM] = { 0x80000000, 0x4000 } [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
}; };
static void riscv_sifive_e_init(MachineState *machine) static void sifive_e_machine_init(MachineState *machine)
{ {
const struct MemmapEntry *memmap = sifive_e_memmap; const struct MemmapEntry *memmap = sifive_e_memmap;
@ -147,7 +147,7 @@ static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc); MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "RISC-V Board compatible with SiFive E SDK"; mc->desc = "RISC-V Board compatible with SiFive E SDK";
mc->init = riscv_sifive_e_init; mc->init = sifive_e_machine_init;
mc->max_cpus = 1; mc->max_cpus = 1;
mc->default_cpu_type = SIFIVE_E_CPU; mc->default_cpu_type = SIFIVE_E_CPU;
} }
@ -167,7 +167,7 @@ static void sifive_e_machine_init_register_types(void)
type_init(sifive_e_machine_init_register_types) type_init(sifive_e_machine_init_register_types)
static void riscv_sifive_e_soc_init(Object *obj) static void sifive_e_soc_init(Object *obj)
{ {
MachineState *ms = MACHINE(qdev_get_machine()); MachineState *ms = MACHINE(qdev_get_machine());
SiFiveESoCState *s = RISCV_E_SOC(obj); SiFiveESoCState *s = RISCV_E_SOC(obj);
@ -179,7 +179,7 @@ static void riscv_sifive_e_soc_init(Object *obj)
TYPE_SIFIVE_GPIO); TYPE_SIFIVE_GPIO);
} }
static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
{ {
MachineState *ms = MACHINE(qdev_get_machine()); MachineState *ms = MACHINE(qdev_get_machine());
const struct MemmapEntry *memmap = sifive_e_memmap; const struct MemmapEntry *memmap = sifive_e_memmap;
@ -262,26 +262,26 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
&s->xip_mem); &s->xip_mem);
} }
static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data) static void sifive_e_soc_class_init(ObjectClass *oc, void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = riscv_sifive_e_soc_realize; dc->realize = sifive_e_soc_realize;
/* Reason: Uses serial_hds in realize function, thus can't be used twice */ /* Reason: Uses serial_hds in realize function, thus can't be used twice */
dc->user_creatable = false; dc->user_creatable = false;
} }
static const TypeInfo riscv_sifive_e_soc_type_info = { static const TypeInfo sifive_e_soc_type_info = {
.name = TYPE_RISCV_E_SOC, .name = TYPE_RISCV_E_SOC,
.parent = TYPE_DEVICE, .parent = TYPE_DEVICE,
.instance_size = sizeof(SiFiveESoCState), .instance_size = sizeof(SiFiveESoCState),
.instance_init = riscv_sifive_e_soc_init, .instance_init = sifive_e_soc_init,
.class_init = riscv_sifive_e_soc_class_init, .class_init = sifive_e_soc_class_init,
}; };
static void riscv_sifive_e_soc_register_types(void) static void sifive_e_soc_register_types(void)
{ {
type_register_static(&riscv_sifive_e_soc_type_info); type_register_static(&sifive_e_soc_type_info);
} }
type_init(riscv_sifive_e_soc_register_types) type_init(sifive_e_soc_register_types)