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Enable all alignment checks

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3404 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2007-10-17 17:34:57 +00:00
parent dbe7fb91e1
commit 8f577d3d29
1 changed files with 5 additions and 48 deletions
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53
target-sparc/translate.c
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@ -346,13 +346,6 @@ GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf); GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf); GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
#ifdef ALIGN_7_BUGS_FIXED
#else
#ifndef CONFIG_USER_ONLY
#define gen_op_check_align_T0_7()
#endif
#endif
/* moves */ /* moves */
#ifdef CONFIG_USER_ONLY #ifdef CONFIG_USER_ONLY
#define supervisor(dc) 0 #define supervisor(dc) 0
@ -2941,9 +2934,7 @@ static void disas_sparc_insn(DisasContext * dc)
(xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
switch (xop) { switch (xop) {
case 0x0: /* load word */ case 0x0: /* load word */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3(); gen_op_check_align_T0_3();
#endif
#ifndef TARGET_SPARC64 #ifndef TARGET_SPARC64
gen_op_ldst(ld); gen_op_ldst(ld);
#else #else
@ -2954,15 +2945,13 @@ static void disas_sparc_insn(DisasContext * dc)
gen_op_ldst(ldub); gen_op_ldst(ldub);
break; break;
case 0x2: /* load unsigned halfword */ case 0x2: /* load unsigned halfword */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_1(); gen_op_check_align_T0_1();
#endif
gen_op_ldst(lduh); gen_op_ldst(lduh);
break; break;
case 0x3: /* load double word */ case 0x3: /* load double word */
gen_op_check_align_T0_7();
if (rd & 1) if (rd & 1)
goto illegal_insn; goto illegal_insn;
gen_op_check_align_T0_7();
gen_op_ldst(ldd); gen_op_ldst(ldd);
gen_movl_T0_reg(rd + 1); gen_movl_T0_reg(rd + 1);
break; break;
@ -2970,18 +2959,14 @@ static void disas_sparc_insn(DisasContext * dc)
gen_op_ldst(ldsb); gen_op_ldst(ldsb);
break; break;
case 0xa: /* load signed halfword */ case 0xa: /* load signed halfword */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_1(); gen_op_check_align_T0_1();
#endif
gen_op_ldst(ldsh); gen_op_ldst(ldsh);
break; break;
case 0xd: /* ldstub -- XXX: should be atomically */ case 0xd: /* ldstub -- XXX: should be atomically */
gen_op_ldst(ldstub); gen_op_ldst(ldstub);
break; break;
case 0x0f: /* swap register with memory. Also atomically */ case 0x0f: /* swap register with memory. Also atomically */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3(); gen_op_check_align_T0_3();
#endif
gen_movl_reg_T1(rd); gen_movl_reg_T1(rd);
gen_op_ldst(swap); gen_op_ldst(swap);
break; break;
@ -2992,9 +2977,8 @@ static void disas_sparc_insn(DisasContext * dc)
goto illegal_insn; goto illegal_insn;
if (!supervisor(dc)) if (!supervisor(dc))
goto priv_insn; goto priv_insn;
#elif CONFIG_USER_ONLY
gen_op_check_align_T0_3();
#endif #endif
gen_op_check_align_T0_3();
gen_ld_asi(insn, 4, 0); gen_ld_asi(insn, 4, 0);
break; break;
case 0x11: /* load unsigned byte alternate */ case 0x11: /* load unsigned byte alternate */
@ -3012,9 +2996,8 @@ static void disas_sparc_insn(DisasContext * dc)
goto illegal_insn; goto illegal_insn;
if (!supervisor(dc)) if (!supervisor(dc))
goto priv_insn; goto priv_insn;
#elif CONFIG_USER_ONLY
gen_op_check_align_T0_1();
#endif #endif
gen_op_check_align_T0_1();
gen_ld_asi(insn, 2, 0); gen_ld_asi(insn, 2, 0);
break; break;
case 0x13: /* load double word alternate */ case 0x13: /* load double word alternate */
@ -3045,9 +3028,8 @@ static void disas_sparc_insn(DisasContext * dc)
goto illegal_insn; goto illegal_insn;
if (!supervisor(dc)) if (!supervisor(dc))
goto priv_insn; goto priv_insn;
#elif CONFIG_USER_ONLY
gen_op_check_align_T0_1();
#endif #endif
gen_op_check_align_T0_1();
gen_ld_asi(insn, 2, 1); gen_ld_asi(insn, 2, 1);
break; break;
case 0x1d: /* ldstuba -- XXX: should be atomically */ case 0x1d: /* ldstuba -- XXX: should be atomically */
@ -3065,9 +3047,8 @@ static void disas_sparc_insn(DisasContext * dc)
goto illegal_insn; goto illegal_insn;
if (!supervisor(dc)) if (!supervisor(dc))
goto priv_insn; goto priv_insn;
#elif CONFIG_USER_ONLY
gen_op_check_align_T0_3();
#endif #endif
gen_op_check_align_T0_3();
gen_movl_reg_T1(rd); gen_movl_reg_T1(rd);
gen_swap_asi(insn); gen_swap_asi(insn);
break; break;
@ -3081,9 +3062,7 @@ static void disas_sparc_insn(DisasContext * dc)
#endif #endif
#ifdef TARGET_SPARC64 #ifdef TARGET_SPARC64
case 0x08: /* V9 ldsw */ case 0x08: /* V9 ldsw */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3(); gen_op_check_align_T0_3();
#endif
gen_op_ldst(ldsw); gen_op_ldst(ldsw);
break; break;
case 0x0b: /* V9 ldx */ case 0x0b: /* V9 ldx */
@ -3091,9 +3070,7 @@ static void disas_sparc_insn(DisasContext * dc)
gen_op_ldst(ldx); gen_op_ldst(ldx);
break; break;
case 0x18: /* V9 ldswa */ case 0x18: /* V9 ldswa */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3(); gen_op_check_align_T0_3();
#endif
gen_ld_asi(insn, 4, 1); gen_ld_asi(insn, 4, 1);
break; break;
case 0x1b: /* V9 ldxa */ case 0x1b: /* V9 ldxa */
@ -3103,9 +3080,7 @@ static void disas_sparc_insn(DisasContext * dc)
case 0x2d: /* V9 prefetch, no effect */ case 0x2d: /* V9 prefetch, no effect */
goto skip_move; goto skip_move;
case 0x30: /* V9 ldfa */ case 0x30: /* V9 ldfa */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3(); gen_op_check_align_T0_3();
#endif
gen_ldf_asi(insn, 4); gen_ldf_asi(insn, 4);
goto skip_move; goto skip_move;
case 0x33: /* V9 lddfa */ case 0x33: /* V9 lddfa */
@ -3129,16 +3104,12 @@ static void disas_sparc_insn(DisasContext * dc)
goto jmp_insn; goto jmp_insn;
switch (xop) { switch (xop) {
case 0x20: /* load fpreg */ case 0x20: /* load fpreg */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3(); gen_op_check_align_T0_3();
#endif
gen_op_ldst(ldf); gen_op_ldst(ldf);
gen_op_store_FT0_fpr(rd); gen_op_store_FT0_fpr(rd);
break; break;
case 0x21: /* load fsr */ case 0x21: /* load fsr */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3(); gen_op_check_align_T0_3();
#endif
gen_op_ldst(ldf); gen_op_ldst(ldf);
gen_op_ldfsr(); gen_op_ldfsr();
break; break;
@ -3157,18 +3128,14 @@ static void disas_sparc_insn(DisasContext * dc)
gen_movl_reg_T1(rd); gen_movl_reg_T1(rd);
switch (xop) { switch (xop) {
case 0x4: case 0x4:
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3(); gen_op_check_align_T0_3();
#endif
gen_op_ldst(st); gen_op_ldst(st);
break; break;
case 0x5: case 0x5:
gen_op_ldst(stb); gen_op_ldst(stb);
break; break;
case 0x6: case 0x6:
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_1(); gen_op_check_align_T0_1();
#endif
gen_op_ldst(sth); gen_op_ldst(sth);
break; break;
case 0x7: case 0x7:
@ -3187,9 +3154,7 @@ static void disas_sparc_insn(DisasContext * dc)
if (!supervisor(dc)) if (!supervisor(dc))
goto priv_insn; goto priv_insn;
#endif #endif
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3(); gen_op_check_align_T0_3();
#endif
gen_st_asi(insn, 4); gen_st_asi(insn, 4);
break; break;
case 0x15: case 0x15:
@ -3208,9 +3173,7 @@ static void disas_sparc_insn(DisasContext * dc)
if (!supervisor(dc)) if (!supervisor(dc))
goto priv_insn; goto priv_insn;
#endif #endif
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_1(); gen_op_check_align_T0_1();
#endif
gen_st_asi(insn, 2); gen_st_asi(insn, 2);
break; break;
case 0x17: case 0x17:
@ -3246,9 +3209,7 @@ static void disas_sparc_insn(DisasContext * dc)
goto jmp_insn; goto jmp_insn;
switch (xop) { switch (xop) {
case 0x24: case 0x24:
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3(); gen_op_check_align_T0_3();
#endif
gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT0(rd);
gen_op_ldst(stf); gen_op_ldst(stf);
break; break;
@ -3279,9 +3240,7 @@ static void disas_sparc_insn(DisasContext * dc)
switch (xop) { switch (xop) {
#ifdef TARGET_SPARC64 #ifdef TARGET_SPARC64
case 0x34: /* V9 stfa */ case 0x34: /* V9 stfa */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3(); gen_op_check_align_T0_3();
#endif
gen_op_load_fpr_FT0(rd); gen_op_load_fpr_FT0(rd);
gen_stf_asi(insn, 4); gen_stf_asi(insn, 4);
break; break;
@ -3291,9 +3250,7 @@ static void disas_sparc_insn(DisasContext * dc)
gen_stf_asi(insn, 8); gen_stf_asi(insn, 8);
break; break;
case 0x3c: /* V9 casa */ case 0x3c: /* V9 casa */
#ifdef CONFIG_USER_ONLY
gen_op_check_align_T0_3(); gen_op_check_align_T0_3();
#endif
flush_T2(dc); flush_T2(dc);
gen_movl_reg_T2(rd); gen_movl_reg_T2(rd);
gen_cas_asi(insn); gen_cas_asi(insn);