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target-alpha: Convert opcode 0x1A to source/sink

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Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2014-03-19 00:12:43 -07:00
parent 89fe090bb3
commit 8f56ced8aa
1 changed files with 4 additions and 5 deletions
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9
target-alpha/translate.c
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@ -2735,6 +2735,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
goto invalid_opc; goto invalid_opc;
} }
break; break;
case 0x19: case 0x19:
/* HW_MFPR (PALcode) */ /* HW_MFPR (PALcode) */
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
@ -2743,14 +2744,12 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
#else #else
goto invalid_opc; goto invalid_opc;
#endif #endif
case 0x1A: case 0x1A:
/* JMP, JSR, RET, JSR_COROUTINE. These only differ by the branch /* JMP, JSR, RET, JSR_COROUTINE. These only differ by the branch
prediction stack action, which of course we don't implement. */ prediction stack action, which of course we don't implement. */
if (rb != 31) { vb = load_gpr(ctx, rb);
tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3); tcg_gen_andi_i64(cpu_pc, vb, ~3);
} else {
tcg_gen_movi_i64(cpu_pc, 0);
}
if (ra != 31) { if (ra != 31) {
tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
} }