Merge remote-tracking branch 'afaerber/memory-ioport' into staging
* afaerber/memory-ioport: acpi_piix4: Do not use old_portio-style callbacks xen_platform: Do not use old_portio-style callbacks hw/dma.c: Fix conversion of ioport_register* to MemoryRegion Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
commit
8ec12ec734
@ -531,68 +531,58 @@ static const MemoryRegionOps piix4_gpe_ops = {
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static uint32_t pci_up_read(void *opaque, uint32_t addr)
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static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size)
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{
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PIIX4PMState *s = opaque;
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uint32_t val;
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uint32_t val = 0;
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/* Manufacture an "up" value to cause a device check on any hotplug
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* slot with a device. Extra device checks are harmless. */
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val = s->pci0_slot_device_present & s->pci0_hotplug_enable;
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switch (addr) {
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case PCI_UP_BASE - PCI_HOTPLUG_ADDR:
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/* Manufacture an "up" value to cause a device check on any hotplug
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* slot with a device. Extra device checks are harmless. */
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val = s->pci0_slot_device_present & s->pci0_hotplug_enable;
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PIIX4_DPRINTF("pci_up_read %x\n", val);
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break;
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case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR:
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val = s->pci0_status.down;
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PIIX4_DPRINTF("pci_down_read %x\n", val);
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break;
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case PCI_EJ_BASE - PCI_HOTPLUG_ADDR:
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/* No feature defined yet */
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PIIX4_DPRINTF("pci_features_read %x\n", val);
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break;
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case PCI_RMV_BASE - PCI_HOTPLUG_ADDR:
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val = s->pci0_hotplug_enable;
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break;
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default:
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break;
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}
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PIIX4_DPRINTF("pci_up_read %x\n", val);
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return val;
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}
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static uint32_t pci_down_read(void *opaque, uint32_t addr)
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static void pci_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned int size)
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{
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PIIX4PMState *s = opaque;
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uint32_t val = s->pci0_status.down;
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PIIX4_DPRINTF("pci_down_read %x\n", val);
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return val;
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}
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static uint32_t pci_features_read(void *opaque, uint32_t addr)
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{
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/* No feature defined yet */
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PIIX4_DPRINTF("pci_features_read %x\n", 0);
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return 0;
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}
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static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
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{
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acpi_piix_eject_slot(opaque, val);
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PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
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}
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static uint32_t pcirmv_read(void *opaque, uint32_t addr)
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{
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PIIX4PMState *s = opaque;
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return s->pci0_hotplug_enable;
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switch (addr) {
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case PCI_EJ_BASE - PCI_HOTPLUG_ADDR:
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acpi_piix_eject_slot(opaque, (uint32_t)data);
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PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== % " PRIu64 "\n",
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addr, data);
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break;
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default:
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break;
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}
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}
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static const MemoryRegionOps piix4_pci_ops = {
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.old_portio = (MemoryRegionPortio[]) {
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{
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.offset = PCI_UP_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4,
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.read = pci_up_read,
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},{
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.offset = PCI_DOWN_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4,
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.read = pci_down_read,
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},{
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.offset = PCI_EJ_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4,
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.read = pci_features_read,
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.write = pciej_write,
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},{
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.offset = PCI_RMV_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4,
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.read = pcirmv_read,
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},
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PORTIO_END_OF_LIST()
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},
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.read = pci_read,
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.write = pci_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
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22
hw/dma.c
22
hw/dma.c
@ -201,7 +201,7 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data,
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iport = (nport >> d->dshift) & 0x0f;
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switch (iport) {
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case 0x01: /* command */
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case 0x00: /* command */
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if ((data != 0) && (data & CMD_NOT_SUPPORTED)) {
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dolog("command %"PRIx64" not supported\n", data);
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return;
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@ -209,7 +209,7 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data,
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d->command = data;
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break;
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case 0x02:
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case 0x01:
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ichan = data & 3;
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if (data & 4) {
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d->status |= 1 << (ichan + 4);
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@ -221,7 +221,7 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data,
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DMA_run();
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break;
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case 0x03: /* single mask */
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case 0x02: /* single mask */
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if (data & 4)
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d->mask |= 1 << (data & 3);
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else
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@ -229,7 +229,7 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data,
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DMA_run();
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break;
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case 0x04: /* mode */
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case 0x03: /* mode */
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{
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ichan = data & 3;
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#ifdef DEBUG_DMA
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@ -248,23 +248,23 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data,
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break;
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}
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case 0x05: /* clear flip flop */
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case 0x04: /* clear flip flop */
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d->flip_flop = 0;
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break;
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case 0x06: /* reset */
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case 0x05: /* reset */
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d->flip_flop = 0;
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d->mask = ~0;
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d->status = 0;
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d->command = 0;
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break;
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case 0x07: /* clear mask for all channels */
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case 0x06: /* clear mask for all channels */
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d->mask = 0;
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DMA_run();
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break;
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case 0x08: /* write mask for all channels */
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case 0x07: /* write mask for all channels */
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d->mask = data;
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DMA_run();
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break;
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@ -289,11 +289,11 @@ static uint64_t read_cont(void *opaque, hwaddr nport, unsigned size)
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iport = (nport >> d->dshift) & 0x0f;
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switch (iport) {
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case 0x08: /* status */
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case 0x00: /* status */
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val = d->status;
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d->status &= 0xf0;
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break;
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case 0x0f: /* mask */
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case 0x01: /* mask */
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val = d->mask;
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break;
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default:
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@ -468,7 +468,7 @@ void DMA_schedule(int nchan)
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static void dma_reset(void *opaque)
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{
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struct dma_cont *d = opaque;
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write_cont(d, (0x06 << d->dshift), 0, 1);
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write_cont(d, (0x05 << d->dshift), 0, 1);
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}
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static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len)
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@ -279,7 +279,8 @@ static void platform_fixed_ioport_init(PCIXenPlatformState* s)
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/* Xen Platform PCI Device */
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static uint32_t xen_platform_ioport_readb(void *opaque, uint32_t addr)
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static uint64_t xen_platform_ioport_readb(void *opaque, hwaddr addr,
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unsigned int size)
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{
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if (addr == 0) {
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return platform_fixed_ioport_readb(opaque, 0);
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@ -288,30 +289,28 @@ static uint32_t xen_platform_ioport_readb(void *opaque, uint32_t addr)
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}
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}
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static void xen_platform_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
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static void xen_platform_ioport_writeb(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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PCIXenPlatformState *s = opaque;
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switch (addr) {
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case 0: /* Platform flags */
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platform_fixed_ioport_writeb(opaque, 0, val);
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platform_fixed_ioport_writeb(opaque, 0, (uint32_t)val);
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break;
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case 8:
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log_writeb(s, val);
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log_writeb(s, (uint32_t)val);
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break;
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default:
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break;
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}
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}
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static MemoryRegionPortio xen_pci_portio[] = {
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{ 0, 0x100, 1, .read = xen_platform_ioport_readb, },
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{ 0, 0x100, 1, .write = xen_platform_ioport_writeb, },
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PORTIO_END_OF_LIST()
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};
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static const MemoryRegionOps xen_pci_io_ops = {
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.old_portio = xen_pci_portio,
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.read = xen_platform_ioport_readb,
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.write = xen_platform_ioport_writeb,
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.impl.min_access_size = 1,
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.impl.max_access_size = 1,
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};
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static void platform_ioport_bar_setup(PCIXenPlatformState *d)
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