Prepare MacOS ROM support:
- add RTR instruction - fix unaligned access requirement - fix ATC bit (68040 MMU) -----BEGIN PGP SIGNATURE----- iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmBKlyMSHGxhdXJlbnRA dml2aWVyLmV1AAoJEPMMOL0/L748RNYP/A/5lAz3t91tx65RX12pYCMNzyhtfL+q UZeLx2YFJpruKEpcjS3a7/gUP/KoTf24CQOsAE6ETIsSshxBBeM+BF5/TaBlSv5G tc68GNNp7fSqPakqUG1WOsMeFjkl+2x52vWGRIef4b/fEHrjuOwPoN7SxTqcBCAa f9/A+9E0mTKbuZmKi+cYwk9LM2IadQndvV/M4UVBn6arWSQhkpuXg5t6IGxfAWQG C9PAuCWJy/MeCua7gkqWOlB3oBNBI3aVY1JZjvjTh2bUqXuZ2gnpkXpROrmJ5d44 LFn1zWRuhL9Lpu/Cf6i5a2gnDrc3AE7s4cfOII1VpmVoc8QEfUcPC2IGA2OCG6x/ MLNr5pRbHn/2pEWt9qsjePBq21AciODGSsz2DQb8hGlDVlFW1b2cD0W5wubxAX9D YfRDMTq5CeTCELnuBfd2Wd/Isg+ucmRH9wo0TQ4gxiRw7r1iZbPa/OUcbVeJmFCo u4YSHLjzEWHdMsKdAXdc75eSyaHn0DcdCaCWoGCa5CUMIUeqBsO09EeaTBSPMmk4 azD658vpSiscRaYntXDsFPnKxYYfgFm9JiX0t5TBAeIX7WvXTNY3sws64FBsucEL pdM+3w+slwRWT2033Rekt4TZHYzCJYLTs4uCyGtXZVL373whedvS8H29iGXsfSQ0 pM2r7u/BF7kc =Xrpn -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-6.0-pull-request' into staging Prepare MacOS ROM support: - add RTR instruction - fix unaligned access requirement - fix ATC bit (68040 MMU) # gpg: Signature made Thu 11 Mar 2021 22:18:11 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-6.0-pull-request: target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature target/m68k: reformat m68k_features enum target/m68k: don't set SSW ATC bit for physical bus errors target/m68k: implement rtr instruction Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
8e6bc6cdc8
@ -161,6 +161,7 @@ static void m68020_cpu_initfn(Object *obj)
|
||||
m68k_set_feature(env, M68K_FEATURE_CAS);
|
||||
m68k_set_feature(env, M68K_FEATURE_CHK2);
|
||||
m68k_set_feature(env, M68K_FEATURE_MSP);
|
||||
m68k_set_feature(env, M68K_FEATURE_UNALIGNED_DATA);
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@ -475,36 +475,60 @@ void do_m68k_semihosting(CPUM68KState *env, int nr);
|
||||
*/
|
||||
|
||||
enum m68k_features {
|
||||
M68K_FEATURE_M68000, /* Base m68k instruction set */
|
||||
/* Base m68k instruction set */
|
||||
M68K_FEATURE_M68000,
|
||||
M68K_FEATURE_M68010,
|
||||
M68K_FEATURE_M68020,
|
||||
M68K_FEATURE_M68030,
|
||||
M68K_FEATURE_M68040,
|
||||
M68K_FEATURE_M68060,
|
||||
M68K_FEATURE_CF_ISA_A, /* Base Coldfire set Rev A. */
|
||||
M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */
|
||||
M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */
|
||||
M68K_FEATURE_BRAL, /* BRA with Long branch. (680[2346]0, ISA A+ or B). */
|
||||
/* Base Coldfire set Rev A. */
|
||||
M68K_FEATURE_CF_ISA_A,
|
||||
/* (ISA B or C). */
|
||||
M68K_FEATURE_CF_ISA_B,
|
||||
/* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */
|
||||
M68K_FEATURE_CF_ISA_APLUSC,
|
||||
/* BRA with Long branch. (680[2346]0, ISA A+ or B). */
|
||||
M68K_FEATURE_BRAL,
|
||||
M68K_FEATURE_CF_FPU,
|
||||
M68K_FEATURE_CF_MAC,
|
||||
M68K_FEATURE_CF_EMAC,
|
||||
M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */
|
||||
M68K_FEATURE_USP, /* User Stack Pointer. (680[012346]0, ISA A+, B or C).*/
|
||||
M68K_FEATURE_MSP, /* Master Stack Pointer. (680[234]0) */
|
||||
M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */
|
||||
M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */
|
||||
M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */
|
||||
M68K_FEATURE_LONG_MULDIV, /* 32 bit mul/div. (680[2346]0, and CPU32) */
|
||||
M68K_FEATURE_QUAD_MULDIV, /* 64 bit mul/div. (680[2346]0, and CPU32) */
|
||||
M68K_FEATURE_BCCL, /* Bcc with Long branches. (680[2346]0, and CPU32) */
|
||||
M68K_FEATURE_BITFIELD, /* BFxxx Bit field insns. (680[2346]0) */
|
||||
M68K_FEATURE_FPU, /* fpu insn. (680[46]0) */
|
||||
M68K_FEATURE_CAS, /* CAS/CAS2[WL] insns. (680[2346]0) */
|
||||
M68K_FEATURE_BKPT, /* BKPT insn. (680[12346]0, and CPU32) */
|
||||
M68K_FEATURE_RTD, /* RTD insn. (680[12346]0, and CPU32) */
|
||||
M68K_FEATURE_CHK2, /* CHK2 insn. (680[2346]0, and CPU32) */
|
||||
M68K_FEATURE_MOVEP, /* MOVEP insn. (680[01234]0, and CPU32) */
|
||||
M68K_FEATURE_MOVEC, /* MOVEC insn. (from 68010) */
|
||||
/* Revision B EMAC (dual accumulate). */
|
||||
M68K_FEATURE_CF_EMAC_B,
|
||||
/* User Stack Pointer. (680[012346]0, ISA A+, B or C). */
|
||||
M68K_FEATURE_USP,
|
||||
/* Master Stack Pointer. (680[234]0) */
|
||||
M68K_FEATURE_MSP,
|
||||
/* 68020+ full extension word. */
|
||||
M68K_FEATURE_EXT_FULL,
|
||||
/* word sized address index registers. */
|
||||
M68K_FEATURE_WORD_INDEX,
|
||||
/* scaled address index registers. */
|
||||
M68K_FEATURE_SCALED_INDEX,
|
||||
/* 32 bit mul/div. (680[2346]0, and CPU32) */
|
||||
M68K_FEATURE_LONG_MULDIV,
|
||||
/* 64 bit mul/div. (680[2346]0, and CPU32) */
|
||||
M68K_FEATURE_QUAD_MULDIV,
|
||||
/* Bcc with Long branches. (680[2346]0, and CPU32) */
|
||||
M68K_FEATURE_BCCL,
|
||||
/* BFxxx Bit field insns. (680[2346]0) */
|
||||
M68K_FEATURE_BITFIELD,
|
||||
/* fpu insn. (680[46]0) */
|
||||
M68K_FEATURE_FPU,
|
||||
/* CAS/CAS2[WL] insns. (680[2346]0) */
|
||||
M68K_FEATURE_CAS,
|
||||
/* BKPT insn. (680[12346]0, and CPU32) */
|
||||
M68K_FEATURE_BKPT,
|
||||
/* RTD insn. (680[12346]0, and CPU32) */
|
||||
M68K_FEATURE_RTD,
|
||||
/* CHK2 insn. (680[2346]0, and CPU32) */
|
||||
M68K_FEATURE_CHK2,
|
||||
/* MOVEP insn. (680[01234]0, and CPU32) */
|
||||
M68K_FEATURE_MOVEP,
|
||||
/* MOVEC insn. (from 68010) */
|
||||
M68K_FEATURE_MOVEC,
|
||||
/* Unaligned data accesses (680[2346]0) */
|
||||
M68K_FEATURE_UNALIGNED_DATA,
|
||||
};
|
||||
|
||||
static inline int m68k_feature(CPUM68KState *env, int feature)
|
||||
|
||||
@ -348,7 +348,10 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw)
|
||||
cpu_m68k_set_sr(env, sr);
|
||||
sp = env->aregs[7];
|
||||
|
||||
if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) {
|
||||
sp &= ~1;
|
||||
}
|
||||
|
||||
if (cs->exception_index == EXCP_ACCESS) {
|
||||
if (env->mmu.fault) {
|
||||
cpu_abort(cs, "DOUBLE MMU FAULT\n");
|
||||
@ -468,7 +471,17 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
|
||||
|
||||
if (m68k_feature(env, M68K_FEATURE_M68040)) {
|
||||
env->mmu.mmusr = 0;
|
||||
|
||||
/*
|
||||
* According to the MC68040 users manual the ATC bit of the SSW is
|
||||
* used to distinguish between ATC faults and physical bus errors.
|
||||
* In the case of a bus error e.g. during nubus read from an empty
|
||||
* slot this bit should not be set
|
||||
*/
|
||||
if (response != MEMTX_DECODE_ERROR) {
|
||||
env->mmu.ssw |= M68K_ATC_040;
|
||||
}
|
||||
|
||||
/* FIXME: manage MMU table access error */
|
||||
env->mmu.ssw &= ~M68K_TM_040;
|
||||
if (env->sr & SR_S) { /* SUPERVISOR */
|
||||
|
||||
@ -2969,6 +2969,25 @@ DISAS_INSN(rtd)
|
||||
gen_jmp(s, tmp);
|
||||
}
|
||||
|
||||
DISAS_INSN(rtr)
|
||||
{
|
||||
TCGv tmp;
|
||||
TCGv ccr;
|
||||
TCGv sp;
|
||||
|
||||
sp = tcg_temp_new();
|
||||
ccr = gen_load(s, OS_WORD, QREG_SP, 0, IS_USER(s));
|
||||
tcg_gen_addi_i32(sp, QREG_SP, 2);
|
||||
tmp = gen_load(s, OS_LONG, sp, 0, IS_USER(s));
|
||||
tcg_gen_addi_i32(QREG_SP, sp, 4);
|
||||
tcg_temp_free(sp);
|
||||
|
||||
gen_set_sr(s, ccr, true);
|
||||
tcg_temp_free(ccr);
|
||||
|
||||
gen_jmp(s, tmp);
|
||||
}
|
||||
|
||||
DISAS_INSN(rts)
|
||||
{
|
||||
TCGv tmp;
|
||||
@ -6015,6 +6034,7 @@ void register_m68k_insns (CPUM68KState *env)
|
||||
BASE(nop, 4e71, ffff);
|
||||
INSN(rtd, 4e74, ffff, RTD);
|
||||
BASE(rts, 4e75, ffff);
|
||||
INSN(rtr, 4e77, ffff, M68000);
|
||||
BASE(jump, 4e80, ffc0);
|
||||
BASE(jump, 4ec0, ffc0);
|
||||
INSN(addsubq, 5000, f080, M68000);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user